1 /*
2  * Copyright (c) 2016 MediaTek Inc.
3  * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  */
14 
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 
20 #include "clk-mtk.h"
21 #include "clk-gate.h"
22 
23 #include <dt-bindings/clock/mt6797-clk.h>
24 
25 /*
26  * For some clocks, we don't care what their actual rates are. And these
27  * clocks may change their rate on different products or different scenarios.
28  * So we model these clocks' rate as 0, to denote it's not an actual rate.
29  */
30 
31 static DEFINE_SPINLOCK(mt6797_clk_lock);
32 
33 static const struct mtk_fixed_factor top_fixed_divs[] = {
34 	FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1),
35 	FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
36 	FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
37 	FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
38 	FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
39 	FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
40 	FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
41 	FACTOR(CLK_TOP_SYSPLL_D3_D3, "syspll_d3_d3", "syspll_d3", 1, 3),
42 	FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
43 	FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
44 	FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
45 	FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
46 	FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
47 	FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
48 	FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
49 	FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
50 	FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
51 	FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1),
52 	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
53 	FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
54 	FACTOR(CLK_TOP_SSUSB_PHY_48M_CK, "ssusb_phy_48m_ck", "univpll", 1, 1),
55 	FACTOR(CLK_TOP_USB_PHY48M_CK, "usb_phy48m_ck", "univpll", 1, 1),
56 	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
57 	FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
58 	FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
59 	FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
60 	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
61 	FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 2),
62 	FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
63 	FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8),
64 	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
65 	FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
66 	FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
67 	FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
68 	FACTOR(CLK_TOP_ULPOSC_CK_ORG, "ulposc_ck_org", "ulposc", 1, 1),
69 	FACTOR(CLK_TOP_ULPOSC_CK, "ulposc_ck", "ulposc_ck_org", 1, 3),
70 	FACTOR(CLK_TOP_ULPOSC_D2, "ulposc_d2", "ulposc_ck", 1, 2),
71 	FACTOR(CLK_TOP_ULPOSC_D3, "ulposc_d3", "ulposc_ck", 1, 4),
72 	FACTOR(CLK_TOP_ULPOSC_D4, "ulposc_d4", "ulposc_ck", 1, 8),
73 	FACTOR(CLK_TOP_ULPOSC_D8, "ulposc_d8", "ulposc_ck", 1, 10),
74 	FACTOR(CLK_TOP_ULPOSC_D10, "ulposc_d10", "ulposc_ck_org", 1, 1),
75 	FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
76 	FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
77 	FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
78 	FACTOR(CLK_TOP_MFGPLL_D2, "mfgpll_d2", "mfgpll_ck", 1, 2),
79 	FACTOR(CLK_TOP_IMGPLL_CK, "imgpll_ck", "imgpll", 1, 1),
80 	FACTOR(CLK_TOP_IMGPLL_D2, "imgpll_d2", "imgpll_ck", 1, 2),
81 	FACTOR(CLK_TOP_IMGPLL_D4, "imgpll_d4", "imgpll_ck", 1, 4),
82 	FACTOR(CLK_TOP_CODECPLL_CK, "codecpll_ck", "codecpll", 1, 1),
83 	FACTOR(CLK_TOP_CODECPLL_D2, "codecpll_d2", "codecpll_ck", 1, 2),
84 	FACTOR(CLK_TOP_VDECPLL_CK, "vdecpll_ck", "vdecpll", 1, 1),
85 	FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
86 	FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
87 	FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
88 	FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8),
89 	FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16),
90 	FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
91 	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
92 	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4),
93 	FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll_ck", 1, 8),
94 };
95 
96 static const char * const axi_parents[] = {
97 	"clk26m",
98 	"syspll_d7",
99 	"ulposc_axi_ck_mux",
100 };
101 
102 static const char * const ulposc_axi_ck_mux_parents[] = {
103 	"syspll1_d4",
104 	"ulposc_axi_ck_mux_pre",
105 };
106 
107 static const char * const ulposc_axi_ck_mux_pre_parents[] = {
108 	"ulposc_d2",
109 	"ulposc_d3",
110 };
111 
112 static const char * const ddrphycfg_parents[] = {
113 	"clk26m",
114 	"syspll3_d2",
115 	"syspll2_d4",
116 	"syspll1_d8",
117 };
118 
119 static const char * const mm_parents[] = {
120 	"clk26m",
121 	"imgpll_ck",
122 	"univpll1_d2",
123 	"syspll1_d2",
124 };
125 
126 static const char * const pwm_parents[] = {
127 	"clk26m",
128 	"univpll2_d4",
129 	"ulposc_d2",
130 	"ulposc_d3",
131 	"ulposc_d8",
132 	"ulposc_d10",
133 	"ulposc_d4",
134 };
135 
136 static const char * const vdec_parents[] = {
137 	"clk26m",
138 	"vdecpll_ck",
139 	"imgpll_ck",
140 	"syspll_d3",
141 	"univpll_d5",
142 	"clk26m",
143 	"clk26m",
144 };
145 
146 static const char * const venc_parents[] = {
147 	"clk26m",
148 	"codecpll_ck",
149 	"syspll_d3",
150 };
151 
152 static const char * const mfg_parents[] = {
153 	"clk26m",
154 	"mfgpll_ck",
155 	"syspll_d3",
156 	"univpll_d3",
157 };
158 
159 static const char * const camtg[] = {
160 	"clk26m",
161 	"univpll_d26",
162 	"univpll2_d2",
163 };
164 
165 static const char * const uart_parents[] = {
166 	"clk26m",
167 	"univpll2_d8",
168 };
169 
170 static const char * const spi_parents[] = {
171 	"clk26m",
172 	"syspll3_d2",
173 	"syspll2_d4",
174 	"ulposc_spi_ck_mux",
175 };
176 
177 static const char * const ulposc_spi_ck_mux_parents[] = {
178 	"ulposc_d2",
179 	"ulposc_d3",
180 };
181 
182 static const char * const usb20_parents[] = {
183 	"clk26m",
184 	"univpll1_d8",
185 	"syspll4_d2",
186 };
187 
188 static const char * const msdc50_0_hclk_parents[] = {
189 	"clk26m",
190 	"syspll1_d2",
191 	"syspll2_d2",
192 	"syspll4_d2",
193 };
194 
195 static const char * const msdc50_0_parents[] = {
196 	"clk26m",
197 	"msdcpll",
198 	"syspll_d3",
199 	"univpll1_d4",
200 	"syspll2_d2",
201 	"syspll_d7",
202 	"msdcpll_d2",
203 	"univpll1_d2",
204 	"univpll_d3",
205 };
206 
207 static const char * const msdc30_1_parents[] = {
208 	"clk26m",
209 	"univpll2_d2",
210 	"msdcpll_d2",
211 	"univpll1_d4",
212 	"syspll2_d2",
213 	"syspll_d7",
214 	"univpll_d7",
215 };
216 
217 static const char * const msdc30_2_parents[] = {
218 	"clk26m",
219 	"univpll2_d8",
220 	"syspll2_d8",
221 	"syspll1_d8",
222 	"msdcpll_d8",
223 	"syspll3_d4",
224 	"univpll_d26",
225 };
226 
227 static const char * const audio_parents[] = {
228 	"clk26m",
229 	"syspll3_d4",
230 	"syspll4_d4",
231 	"syspll1_d16",
232 };
233 
234 static const char * const aud_intbus_parents[] = {
235 	"clk26m",
236 	"syspll1_d4",
237 	"syspll4_d2",
238 };
239 
240 static const char * const pmicspi_parents[] = {
241 	"clk26m",
242 	"univpll_d26",
243 	"syspll3_d4",
244 	"syspll1_d8",
245 	"ulposc_d4",
246 	"ulposc_d8",
247 	"syspll2_d8",
248 };
249 
250 static const char * const scp_parents[] = {
251 	"clk26m",
252 	"syspll_d3",
253 	"ulposc_ck",
254 	"univpll_d5",
255 };
256 
257 static const char * const atb_parents[] = {
258 	"clk26m",
259 	"syspll1_d2",
260 	"syspll_d5",
261 };
262 
263 static const char * const mjc_parents[] = {
264 	"clk26m",
265 	"imgpll_ck",
266 	"univpll_d5",
267 	"syspll1_d2",
268 };
269 
270 static const char * const dpi0_parents[] = {
271 	"clk26m",
272 	"tvdpll_d2",
273 	"tvdpll_d4",
274 	"tvdpll_d8",
275 	"tvdpll_d16",
276 	"clk26m",
277 	"clk26m",
278 };
279 
280 static const char * const aud_1_parents[] = {
281 	"clk26m",
282 	"apll1_ck",
283 };
284 
285 static const char * const aud_2_parents[] = {
286 	"clk26m",
287 	"apll2_ck",
288 };
289 
290 static const char * const ssusb_top_sys_parents[] = {
291 	"clk26m",
292 	"univpll3_d2",
293 };
294 
295 static const char * const spm_parents[] = {
296 	"clk26m",
297 	"syspll1_d8",
298 };
299 
300 static const char * const bsi_spi_parents[] = {
301 	"clk26m",
302 	"syspll_d3_d3",
303 	"syspll1_d4",
304 	"syspll_d7",
305 };
306 
307 static const char * const audio_h_parents[] = {
308 	"clk26m",
309 	"apll2_ck",
310 	"apll1_ck",
311 	"univpll_d7",
312 };
313 
314 static const char * const mfg_52m_parents[] = {
315 	"clk26m",
316 	"univpll2_d8",
317 	"univpll2_d4",
318 	"univpll2_d4",
319 };
320 
321 static const char * const anc_md32_parents[] = {
322 	"clk26m",
323 	"syspll1_d2",
324 	"univpll_d5",
325 };
326 
327 static const struct mtk_composite top_muxes[] = {
328 	MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre",
329 	    ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1),
330 	MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
331 	    ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
332 	MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
333 	    0x0040, 0, 2),
334 	MUX(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
335 	    0x0040, 16, 2),
336 	MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
337 	    0x0040, 24, 2),
338 	MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
339 	MUX_GATE(CLK_TOP_MUX_VDEC, "vdec_sel", vdec_parents, 0x0050, 8, 3, 15),
340 	MUX_GATE(CLK_TOP_MUX_VENC, "venc_sel", venc_parents, 0x0050, 16, 2, 23),
341 	MUX_GATE(CLK_TOP_MUX_MFG, "mfg_sel", mfg_parents, 0x0050, 24, 2, 31),
342 	MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg, 0x0060, 0, 2, 7),
343 	MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
344 	MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, 0x0060, 16, 2, 23),
345 	MUX(CLK_TOP_MUX_ULPOSC_SPI_CK_MUX, "ulposc_spi_ck_mux",
346 	    ulposc_spi_ck_mux_parents, 0x0060, 18, 1),
347 	MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents,
348 		 0x0060, 24, 2, 31),
349 	MUX(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel",
350 	    msdc50_0_hclk_parents, 0x0070, 8, 2),
351 	MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,
352 		 0x0070, 16, 4, 23),
353 	MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents,
354 		 0x0070, 24, 3, 31),
355 	MUX_GATE(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", msdc30_2_parents,
356 		 0x0080, 0, 3, 7),
357 	MUX_GATE(CLK_TOP_MUX_AUDIO, "audio_sel", audio_parents,
358 		 0x0080, 16, 2, 23),
359 	MUX(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", aud_intbus_parents,
360 	    0x0080, 24, 2),
361 	MUX(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents,
362 	    0x0090, 0, 3),
363 	MUX(CLK_TOP_MUX_SCP, "scp_sel", scp_parents,
364 	    0x0090, 8, 2),
365 	MUX(CLK_TOP_MUX_ATB, "atb_sel", atb_parents,
366 	    0x0090, 16, 2),
367 	MUX_GATE(CLK_TOP_MUX_MJC, "mjc_sel", mjc_parents, 0x0090, 24, 2, 31),
368 	MUX_GATE(CLK_TOP_MUX_DPI0, "dpi0_sel", dpi0_parents, 0x00A0, 0, 3, 7),
369 	MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
370 		 0x00A0, 16, 1, 23),
371 	MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents,
372 		 0x00A0, 24, 1, 31),
373 	MUX(CLK_TOP_MUX_SSUSB_TOP_SYS, "ssusb_top_sys_sel",
374 	    ssusb_top_sys_parents, 0x00B0, 8, 1),
375 	MUX(CLK_TOP_MUX_SPM, "spm_sel", spm_parents,
376 	    0x00C0, 0, 1),
377 	MUX(CLK_TOP_MUX_BSI_SPI, "bsi_spi_sel", bsi_spi_parents,
378 	    0x00C0, 8, 2),
379 	MUX_GATE(CLK_TOP_MUX_AUDIO_H, "audio_h_sel", audio_h_parents,
380 		 0x00C0, 16, 2, 23),
381 	MUX_GATE(CLK_TOP_MUX_ANC_MD32, "anc_md32_sel", anc_md32_parents,
382 		 0x00C0, 24, 2, 31),
383 	MUX(CLK_TOP_MUX_MFG_52M, "mfg_52m_sel", mfg_52m_parents,
384 	    0x0104, 1, 2),
385 };
386 
387 static int mtk_topckgen_init(struct platform_device *pdev)
388 {
389 	struct clk_onecell_data *clk_data;
390 	void __iomem *base;
391 	struct device_node *node = pdev->dev.of_node;
392 	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
393 
394 	base = devm_ioremap_resource(&pdev->dev, res);
395 	if (IS_ERR(base))
396 		return PTR_ERR(base);
397 
398 	clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
399 
400 	mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
401 				 clk_data);
402 
403 	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
404 				    &mt6797_clk_lock, clk_data);
405 
406 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
407 }
408 
409 static const struct mtk_gate_regs infra0_cg_regs = {
410 	.set_ofs = 0x0080,
411 	.clr_ofs = 0x0084,
412 	.sta_ofs = 0x0090,
413 };
414 
415 static const struct mtk_gate_regs infra1_cg_regs = {
416 	.set_ofs = 0x0088,
417 	.clr_ofs = 0x008c,
418 	.sta_ofs = 0x0094,
419 };
420 
421 static const struct mtk_gate_regs infra2_cg_regs = {
422 	.set_ofs = 0x00a8,
423 	.clr_ofs = 0x00ac,
424 	.sta_ofs = 0x00b0,
425 };
426 
427 #define GATE_ICG0(_id, _name, _parent, _shift) {	\
428 	.id = _id,					\
429 	.name = _name,					\
430 	.parent_name = _parent,				\
431 	.regs = &infra0_cg_regs,			\
432 	.shift = _shift,				\
433 	.ops = &mtk_clk_gate_ops_setclr,		\
434 }
435 
436 #define GATE_ICG1(_id, _name, _parent, _shift) {	\
437 	.id = _id,					\
438 	.name = _name,					\
439 	.parent_name = _parent,				\
440 	.regs = &infra1_cg_regs,			\
441 	.shift = _shift,				\
442 	.ops = &mtk_clk_gate_ops_setclr,		\
443 }
444 
445 #define GATE_ICG2(_id, _name, _parent, _shift) {	\
446 	.id = _id,					\
447 	.name = _name,					\
448 	.parent_name = _parent,				\
449 	.regs = &infra2_cg_regs,			\
450 	.shift = _shift,				\
451 	.ops = &mtk_clk_gate_ops_setclr,		\
452 }
453 
454 static const struct mtk_gate infra_clks[] = {
455 	GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0),
456 	GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1),
457 	GATE_ICG0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pmicspi_sel", 2),
458 	GATE_ICG0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pmicspi_sel", 3),
459 	GATE_ICG0(CLK_INFRA_SCP, "infra_scp", "scp_sel", 4),
460 	GATE_ICG0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
461 	GATE_ICG0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
462 	GATE_ICG0(CLK_INFRA_SEJ_13M, "infra_sej_13m", "clk26m", 7),
463 	GATE_ICG0(CLK_INFRA_ICUSB, "infra_icusb", "usb20_sel", 8),
464 	GATE_ICG0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9),
465 	GATE_ICG0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
466 	GATE_ICG0(CLK_INFRA_I2C0, "infra_i2c0", "axi_sel", 11),
467 	GATE_ICG0(CLK_INFRA_I2C1, "infra_i2c1", "axi_sel", 12),
468 	GATE_ICG0(CLK_INFRA_I2C2, "infra_i2c2", "axi_sel", 13),
469 	GATE_ICG0(CLK_INFRA_I2C3, "infra_i2c3", "axi_sel", 14),
470 	GATE_ICG0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15),
471 	GATE_ICG0(CLK_INFRA_PWM1, "infra_pwm1", "axi_sel", 16),
472 	GATE_ICG0(CLK_INFRA_PWM2, "infra_pwm2", "axi_sel", 17),
473 	GATE_ICG0(CLK_INFRA_PWM3, "infra_pwm3", "axi_sel", 18),
474 	GATE_ICG0(CLK_INFRA_PWM4, "infra_pwm4", "axi_sel", 19),
475 	GATE_ICG0(CLK_INFRA_PWM, "infra_pwm", "axi_sel", 21),
476 	GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
477 	GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
478 	GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
479 	GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
480 	GATE_ICG0(CLK_INFRA_MD2MD_CCIF_0, "infra_md2md_ccif_0", "axi_sel", 27),
481 	GATE_ICG0(CLK_INFRA_MD2MD_CCIF_1, "infra_md2md_ccif_1", "axi_sel", 28),
482 	GATE_ICG0(CLK_INFRA_MD2MD_CCIF_2, "infra_md2md_ccif_2", "axi_sel", 29),
483 	GATE_ICG0(CLK_INFRA_FHCTL, "infra_fhctl", "clk26m", 30),
484 	GATE_ICG0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
485 	GATE_ICG1(CLK_INFRA_MD2MD_CCIF_3, "infra_md2md_ccif_3", "axi_sel", 0),
486 	GATE_ICG1(CLK_INFRA_SPI, "infra_spi", "spi_sel", 1),
487 	GATE_ICG1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_sel", 2),
488 	GATE_ICG1(CLK_INFRA_MD2MD_CCIF_4, "infra_md2md_ccif_4", "axi_sel", 3),
489 	GATE_ICG1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc30_1_sel", 4),
490 	GATE_ICG1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc30_2_sel", 5),
491 	GATE_ICG1(CLK_INFRA_MD2MD_CCIF_5, "infra_md2md_ccif_5", "axi_sel", 7),
492 	GATE_ICG1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
493 	GATE_ICG1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
494 	GATE_ICG1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
495 	GATE_ICG1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
496 	GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_0, "infra_ap_c2k_ccif_0",
497 		  "axi_sel", 12),
498 	GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_1, "infra_ap_c2k_ccif_1",
499 		  "axi_sel", 13),
500 	GATE_ICG1(CLK_INFRA_CLDMA, "infra_cldma", "axi_sel", 16),
501 	GATE_ICG1(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "pwm_sel", 17),
502 	GATE_ICG1(CLK_INFRA_AP_DMA, "infra_ap_dma", "axi_sel", 18),
503 	GATE_ICG1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20),
504 	GATE_ICG1(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "mm_sel", 22),
505 	GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
506 	GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
507 	GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
508 	GATE_ICG1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
509 	GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
510 	GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
511 	GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
512 	GATE_ICG2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "axi_sel", 3),
513 	GATE_ICG2(CLK_INFRA_I2C2_ARB, "infra_i2c2_arb", "axi_sel", 4),
514 	GATE_ICG2(CLK_INFRA_I2C3_IMM, "infra_i2c3_imm", "axi_sel", 5),
515 	GATE_ICG2(CLK_INFRA_I2C3_ARB, "infra_i2c3_arb", "axi_sel", 6),
516 	GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
517 	GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
518 	GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
519 	GATE_ICG2(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m", "clk26m", 11),
520 	GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
521 	GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
522 	GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),
523 	GATE_ICG2(CLK_INFRA_AES_TOP0, "infra_aes_top0", "axi_sel", 16),
524 	GATE_ICG2(CLK_INFRA_AES_TOP1, "infra_aes_top1", "axi_sel", 17),
525 	GATE_ICG2(CLK_INFRA_SSUSB_BUS, "infra_ssusb_bus", "axi_sel", 18),
526 	GATE_ICG2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 19),
527 	GATE_ICG2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 20),
528 	GATE_ICG2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 21),
529 	GATE_ICG2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 22),
530 	GATE_ICG2(CLK_INFRA_IRTX, "infra_irtx", "spi_sel", 23),
531 	GATE_ICG2(CLK_INFRA_SSUSB_SYS, "infra_ssusb_sys",
532 		  "ssusb_top_sys_sel", 24),
533 	GATE_ICG2(CLK_INFRA_SSUSB_REF, "infra_ssusb_ref", "clk26m", 9),
534 	GATE_ICG2(CLK_INFRA_AUDIO_26M, "infra_audio_26m", "clk26m", 26),
535 	GATE_ICG2(CLK_INFRA_AUDIO_26M_PAD_TOP, "infra_audio_26m_pad_top",
536 		  "clk26m", 27),
537 	GATE_ICG2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share",
538 		  "axi_sel", 28),
539 	GATE_ICG2(CLK_INFRA_VAD_WRAP_SOC, "infra_vad_wrap_soc", "axi_sel", 29),
540 	GATE_ICG2(CLK_INFRA_DRAMC_CONF, "infra_dramc_conf", "axi_sel", 30),
541 	GATE_ICG2(CLK_INFRA_DRAMC_B_CONF, "infra_dramc_b_conf", "axi_sel", 31),
542 	GATE_ICG1(CLK_INFRA_MFG_VCG, "infra_mfg_vcg", "mfg_52m_sel", 14),
543 };
544 
545 static const struct mtk_fixed_factor infra_fixed_divs[] = {
546 	FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2),
547 };
548 
549 static struct clk_onecell_data *infra_clk_data;
550 
551 static void mtk_infrasys_init_early(struct device_node *node)
552 {
553 	int r, i;
554 
555 	if (!infra_clk_data) {
556 		infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
557 
558 		for (i = 0; i < CLK_INFRA_NR; i++)
559 			infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
560 	}
561 
562 	mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
563 				 infra_clk_data);
564 
565 	r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
566 	if (r)
567 		pr_err("%s(): could not register clock provider: %d\n",
568 		       __func__, r);
569 }
570 
571 CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg",
572 		      mtk_infrasys_init_early);
573 
574 static int mtk_infrasys_init(struct platform_device *pdev)
575 {
576 	int r, i;
577 	struct device_node *node = pdev->dev.of_node;
578 
579 	if (!infra_clk_data) {
580 		infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
581 	} else {
582 		for (i = 0; i < CLK_INFRA_NR; i++) {
583 			if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
584 				infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
585 		}
586 	}
587 
588 	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
589 			       infra_clk_data);
590 	mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
591 				 infra_clk_data);
592 
593 	r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
594 	if (r)
595 		return r;
596 
597 	return 0;
598 }
599 
600 #define MT6797_PLL_FMAX		(3000UL * MHZ)
601 
602 #define CON0_MT6797_RST_BAR	BIT(24)
603 
604 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
605 			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
606 			_pcw_shift, _div_table) {			\
607 	.id = _id,						\
608 	.name = _name,						\
609 	.reg = _reg,						\
610 	.pwr_reg = _pwr_reg,					\
611 	.en_mask = _en_mask,					\
612 	.flags = _flags,					\
613 	.rst_bar_mask = CON0_MT6797_RST_BAR,			\
614 	.fmax = MT6797_PLL_FMAX,				\
615 	.pcwbits = _pcwbits,					\
616 	.pd_reg = _pd_reg,					\
617 	.pd_shift = _pd_shift,					\
618 	.tuner_reg = _tuner_reg,				\
619 	.pcw_reg = _pcw_reg,					\
620 	.pcw_shift = _pcw_shift,				\
621 	.div_table = _div_table,				\
622 }
623 
624 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
625 			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
626 			_pcw_shift)					\
627 		PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
628 			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
629 			NULL)
630 
631 static const struct mtk_pll_data plls[] = {
632 	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000101, PLL_AO,
633 	    21, 0x220, 4, 0x0, 0x224, 0),
634 	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000011, 0, 7,
635 	    0x230, 4, 0x0, 0x234, 14),
636 	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000101, 0, 21,
637 	    0x244, 24, 0x0, 0x244, 0),
638 	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000121, 0, 21,
639 	    0x250, 4, 0x0, 0x254, 0),
640 	PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000121, 0, 21,
641 	    0x260, 4, 0x0, 0x264, 0),
642 	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000121, 0, 21,
643 	    0x270, 4, 0x0, 0x274, 0),
644 	PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000121, 0, 21,
645 	    0x290, 4, 0x0, 0x294, 0),
646 	PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000121, 0, 21,
647 	    0x2E4, 4, 0x0, 0x2E8, 0),
648 	PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000131, 0, 31,
649 	    0x2A0, 4, 0x2A8, 0x2A4, 0),
650 	PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000131, 0, 31,
651 	    0x2B4, 4, 0x2BC, 0x2B8, 0),
652 };
653 
654 static int mtk_apmixedsys_init(struct platform_device *pdev)
655 {
656 	struct clk_onecell_data *clk_data;
657 	struct device_node *node = pdev->dev.of_node;
658 
659 	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
660 	if (!clk_data)
661 		return -ENOMEM;
662 
663 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
664 
665 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
666 }
667 
668 static const struct of_device_id of_match_clk_mt6797[] = {
669 	{
670 		.compatible = "mediatek,mt6797-topckgen",
671 		.data = mtk_topckgen_init,
672 	}, {
673 		.compatible = "mediatek,mt6797-infracfg",
674 		.data = mtk_infrasys_init,
675 	}, {
676 		.compatible = "mediatek,mt6797-apmixedsys",
677 		.data = mtk_apmixedsys_init,
678 	}, {
679 		/* sentinel */
680 	}
681 };
682 
683 static int clk_mt6797_probe(struct platform_device *pdev)
684 {
685 	int (*clk_init)(struct platform_device *);
686 	int r;
687 
688 	clk_init = of_device_get_match_data(&pdev->dev);
689 	if (!clk_init)
690 		return -EINVAL;
691 
692 	r = clk_init(pdev);
693 	if (r)
694 		dev_err(&pdev->dev,
695 			"could not register clock provider: %s: %d\n",
696 			pdev->name, r);
697 
698 	return r;
699 }
700 
701 static struct platform_driver clk_mt6797_drv = {
702 	.probe = clk_mt6797_probe,
703 	.driver = {
704 		.name = "clk-mt6797",
705 		.of_match_table = of_match_clk_mt6797,
706 	},
707 };
708 
709 static int __init clk_mt6797_init(void)
710 {
711 	return platform_driver_register(&clk_mt6797_drv);
712 }
713 
714 arch_initcall(clk_mt6797_init);
715