1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016 MediaTek Inc.
4  * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
5  */
6 
7 #include <linux/of.h>
8 #include <linux/of_address.h>
9 #include <linux/of_device.h>
10 #include <linux/platform_device.h>
11 
12 #include "clk-mtk.h"
13 #include "clk-gate.h"
14 
15 #include <dt-bindings/clock/mt6797-clk.h>
16 
17 /*
18  * For some clocks, we don't care what their actual rates are. And these
19  * clocks may change their rate on different products or different scenarios.
20  * So we model these clocks' rate as 0, to denote it's not an actual rate.
21  */
22 
23 static DEFINE_SPINLOCK(mt6797_clk_lock);
24 
25 static const struct mtk_fixed_factor top_fixed_divs[] = {
26 	FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1),
27 	FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
28 	FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
29 	FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
30 	FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
31 	FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
32 	FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
33 	FACTOR(CLK_TOP_SYSPLL_D3_D3, "syspll_d3_d3", "syspll_d3", 1, 3),
34 	FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
35 	FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
36 	FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
37 	FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
38 	FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
39 	FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
40 	FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
41 	FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
42 	FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
43 	FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1),
44 	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
45 	FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
46 	FACTOR(CLK_TOP_SSUSB_PHY_48M_CK, "ssusb_phy_48m_ck", "univpll", 1, 1),
47 	FACTOR(CLK_TOP_USB_PHY48M_CK, "usb_phy48m_ck", "univpll", 1, 1),
48 	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
49 	FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
50 	FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
51 	FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
52 	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
53 	FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 2),
54 	FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
55 	FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8),
56 	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
57 	FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
58 	FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
59 	FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
60 	FACTOR(CLK_TOP_ULPOSC_CK_ORG, "ulposc_ck_org", "ulposc", 1, 1),
61 	FACTOR(CLK_TOP_ULPOSC_CK, "ulposc_ck", "ulposc_ck_org", 1, 3),
62 	FACTOR(CLK_TOP_ULPOSC_D2, "ulposc_d2", "ulposc_ck", 1, 2),
63 	FACTOR(CLK_TOP_ULPOSC_D3, "ulposc_d3", "ulposc_ck", 1, 4),
64 	FACTOR(CLK_TOP_ULPOSC_D4, "ulposc_d4", "ulposc_ck", 1, 8),
65 	FACTOR(CLK_TOP_ULPOSC_D8, "ulposc_d8", "ulposc_ck", 1, 10),
66 	FACTOR(CLK_TOP_ULPOSC_D10, "ulposc_d10", "ulposc_ck_org", 1, 1),
67 	FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
68 	FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
69 	FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
70 	FACTOR(CLK_TOP_MFGPLL_D2, "mfgpll_d2", "mfgpll_ck", 1, 2),
71 	FACTOR(CLK_TOP_IMGPLL_CK, "imgpll_ck", "imgpll", 1, 1),
72 	FACTOR(CLK_TOP_IMGPLL_D2, "imgpll_d2", "imgpll_ck", 1, 2),
73 	FACTOR(CLK_TOP_IMGPLL_D4, "imgpll_d4", "imgpll_ck", 1, 4),
74 	FACTOR(CLK_TOP_CODECPLL_CK, "codecpll_ck", "codecpll", 1, 1),
75 	FACTOR(CLK_TOP_CODECPLL_D2, "codecpll_d2", "codecpll_ck", 1, 2),
76 	FACTOR(CLK_TOP_VDECPLL_CK, "vdecpll_ck", "vdecpll", 1, 1),
77 	FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
78 	FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
79 	FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
80 	FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8),
81 	FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16),
82 	FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
83 	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
84 	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4),
85 	FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll_ck", 1, 8),
86 };
87 
88 static const char * const axi_parents[] = {
89 	"clk26m",
90 	"syspll_d7",
91 	"ulposc_axi_ck_mux",
92 };
93 
94 static const char * const ulposc_axi_ck_mux_parents[] = {
95 	"syspll1_d4",
96 	"ulposc_axi_ck_mux_pre",
97 };
98 
99 static const char * const ulposc_axi_ck_mux_pre_parents[] = {
100 	"ulposc_d2",
101 	"ulposc_d3",
102 };
103 
104 static const char * const ddrphycfg_parents[] = {
105 	"clk26m",
106 	"syspll3_d2",
107 	"syspll2_d4",
108 	"syspll1_d8",
109 };
110 
111 static const char * const mm_parents[] = {
112 	"clk26m",
113 	"imgpll_ck",
114 	"univpll1_d2",
115 	"syspll1_d2",
116 };
117 
118 static const char * const pwm_parents[] = {
119 	"clk26m",
120 	"univpll2_d4",
121 	"ulposc_d2",
122 	"ulposc_d3",
123 	"ulposc_d8",
124 	"ulposc_d10",
125 	"ulposc_d4",
126 };
127 
128 static const char * const vdec_parents[] = {
129 	"clk26m",
130 	"vdecpll_ck",
131 	"imgpll_ck",
132 	"syspll_d3",
133 	"univpll_d5",
134 	"clk26m",
135 	"clk26m",
136 };
137 
138 static const char * const venc_parents[] = {
139 	"clk26m",
140 	"codecpll_ck",
141 	"syspll_d3",
142 };
143 
144 static const char * const mfg_parents[] = {
145 	"clk26m",
146 	"mfgpll_ck",
147 	"syspll_d3",
148 	"univpll_d3",
149 };
150 
151 static const char * const camtg[] = {
152 	"clk26m",
153 	"univpll_d26",
154 	"univpll2_d2",
155 };
156 
157 static const char * const uart_parents[] = {
158 	"clk26m",
159 	"univpll2_d8",
160 };
161 
162 static const char * const spi_parents[] = {
163 	"clk26m",
164 	"syspll3_d2",
165 	"syspll2_d4",
166 	"ulposc_spi_ck_mux",
167 };
168 
169 static const char * const ulposc_spi_ck_mux_parents[] = {
170 	"ulposc_d2",
171 	"ulposc_d3",
172 };
173 
174 static const char * const usb20_parents[] = {
175 	"clk26m",
176 	"univpll1_d8",
177 	"syspll4_d2",
178 };
179 
180 static const char * const msdc50_0_hclk_parents[] = {
181 	"clk26m",
182 	"syspll1_d2",
183 	"syspll2_d2",
184 	"syspll4_d2",
185 };
186 
187 static const char * const msdc50_0_parents[] = {
188 	"clk26m",
189 	"msdcpll",
190 	"syspll_d3",
191 	"univpll1_d4",
192 	"syspll2_d2",
193 	"syspll_d7",
194 	"msdcpll_d2",
195 	"univpll1_d2",
196 	"univpll_d3",
197 };
198 
199 static const char * const msdc30_1_parents[] = {
200 	"clk26m",
201 	"univpll2_d2",
202 	"msdcpll_d2",
203 	"univpll1_d4",
204 	"syspll2_d2",
205 	"syspll_d7",
206 	"univpll_d7",
207 };
208 
209 static const char * const msdc30_2_parents[] = {
210 	"clk26m",
211 	"univpll2_d8",
212 	"syspll2_d8",
213 	"syspll1_d8",
214 	"msdcpll_d8",
215 	"syspll3_d4",
216 	"univpll_d26",
217 };
218 
219 static const char * const audio_parents[] = {
220 	"clk26m",
221 	"syspll3_d4",
222 	"syspll4_d4",
223 	"syspll1_d16",
224 };
225 
226 static const char * const aud_intbus_parents[] = {
227 	"clk26m",
228 	"syspll1_d4",
229 	"syspll4_d2",
230 };
231 
232 static const char * const pmicspi_parents[] = {
233 	"clk26m",
234 	"univpll_d26",
235 	"syspll3_d4",
236 	"syspll1_d8",
237 	"ulposc_d4",
238 	"ulposc_d8",
239 	"syspll2_d8",
240 };
241 
242 static const char * const scp_parents[] = {
243 	"clk26m",
244 	"syspll_d3",
245 	"ulposc_ck",
246 	"univpll_d5",
247 };
248 
249 static const char * const atb_parents[] = {
250 	"clk26m",
251 	"syspll1_d2",
252 	"syspll_d5",
253 };
254 
255 static const char * const mjc_parents[] = {
256 	"clk26m",
257 	"imgpll_ck",
258 	"univpll_d5",
259 	"syspll1_d2",
260 };
261 
262 static const char * const dpi0_parents[] = {
263 	"clk26m",
264 	"tvdpll_d2",
265 	"tvdpll_d4",
266 	"tvdpll_d8",
267 	"tvdpll_d16",
268 	"clk26m",
269 	"clk26m",
270 };
271 
272 static const char * const aud_1_parents[] = {
273 	"clk26m",
274 	"apll1_ck",
275 };
276 
277 static const char * const aud_2_parents[] = {
278 	"clk26m",
279 	"apll2_ck",
280 };
281 
282 static const char * const ssusb_top_sys_parents[] = {
283 	"clk26m",
284 	"univpll3_d2",
285 };
286 
287 static const char * const spm_parents[] = {
288 	"clk26m",
289 	"syspll1_d8",
290 };
291 
292 static const char * const bsi_spi_parents[] = {
293 	"clk26m",
294 	"syspll_d3_d3",
295 	"syspll1_d4",
296 	"syspll_d7",
297 };
298 
299 static const char * const audio_h_parents[] = {
300 	"clk26m",
301 	"apll2_ck",
302 	"apll1_ck",
303 	"univpll_d7",
304 };
305 
306 static const char * const mfg_52m_parents[] = {
307 	"clk26m",
308 	"univpll2_d8",
309 	"univpll2_d4",
310 	"univpll2_d4",
311 };
312 
313 static const char * const anc_md32_parents[] = {
314 	"clk26m",
315 	"syspll1_d2",
316 	"univpll_d5",
317 };
318 
319 /*
320  * Clock mux ddrphycfg is needed by the DRAM controller. We mark it as
321  * critical as otherwise the system will hang after boot.
322  */
323 static const struct mtk_composite top_muxes[] = {
324 	MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre",
325 	    ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1),
326 	MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
327 	    ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
328 	MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
329 	    0x0040, 0, 2),
330 	MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
331 		  0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
332 	MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
333 	    0x0040, 24, 2),
334 	MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
335 	MUX_GATE(CLK_TOP_MUX_VDEC, "vdec_sel", vdec_parents, 0x0050, 8, 3, 15),
336 	MUX_GATE(CLK_TOP_MUX_VENC, "venc_sel", venc_parents, 0x0050, 16, 2, 23),
337 	MUX_GATE(CLK_TOP_MUX_MFG, "mfg_sel", mfg_parents, 0x0050, 24, 2, 31),
338 	MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg, 0x0060, 0, 2, 7),
339 	MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
340 	MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, 0x0060, 16, 2, 23),
341 	MUX(CLK_TOP_MUX_ULPOSC_SPI_CK_MUX, "ulposc_spi_ck_mux",
342 	    ulposc_spi_ck_mux_parents, 0x0060, 18, 1),
343 	MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents,
344 		 0x0060, 24, 2, 31),
345 	MUX(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel",
346 	    msdc50_0_hclk_parents, 0x0070, 8, 2),
347 	MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,
348 		 0x0070, 16, 4, 23),
349 	MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents,
350 		 0x0070, 24, 3, 31),
351 	MUX_GATE(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", msdc30_2_parents,
352 		 0x0080, 0, 3, 7),
353 	MUX_GATE(CLK_TOP_MUX_AUDIO, "audio_sel", audio_parents,
354 		 0x0080, 16, 2, 23),
355 	MUX(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", aud_intbus_parents,
356 	    0x0080, 24, 2),
357 	MUX(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents,
358 	    0x0090, 0, 3),
359 	MUX(CLK_TOP_MUX_SCP, "scp_sel", scp_parents,
360 	    0x0090, 8, 2),
361 	MUX(CLK_TOP_MUX_ATB, "atb_sel", atb_parents,
362 	    0x0090, 16, 2),
363 	MUX_GATE(CLK_TOP_MUX_MJC, "mjc_sel", mjc_parents, 0x0090, 24, 2, 31),
364 	MUX_GATE(CLK_TOP_MUX_DPI0, "dpi0_sel", dpi0_parents, 0x00A0, 0, 3, 7),
365 	MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
366 		 0x00A0, 16, 1, 23),
367 	MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents,
368 		 0x00A0, 24, 1, 31),
369 	MUX(CLK_TOP_MUX_SSUSB_TOP_SYS, "ssusb_top_sys_sel",
370 	    ssusb_top_sys_parents, 0x00B0, 8, 1),
371 	MUX(CLK_TOP_MUX_SPM, "spm_sel", spm_parents,
372 	    0x00C0, 0, 1),
373 	MUX(CLK_TOP_MUX_BSI_SPI, "bsi_spi_sel", bsi_spi_parents,
374 	    0x00C0, 8, 2),
375 	MUX_GATE(CLK_TOP_MUX_AUDIO_H, "audio_h_sel", audio_h_parents,
376 		 0x00C0, 16, 2, 23),
377 	MUX_GATE(CLK_TOP_MUX_ANC_MD32, "anc_md32_sel", anc_md32_parents,
378 		 0x00C0, 24, 2, 31),
379 	MUX(CLK_TOP_MUX_MFG_52M, "mfg_52m_sel", mfg_52m_parents,
380 	    0x0104, 1, 2),
381 };
382 
383 static int mtk_topckgen_init(struct platform_device *pdev)
384 {
385 	struct clk_onecell_data *clk_data;
386 	void __iomem *base;
387 	struct device_node *node = pdev->dev.of_node;
388 
389 	base = devm_platform_ioremap_resource(pdev, 0);
390 	if (IS_ERR(base))
391 		return PTR_ERR(base);
392 
393 	clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
394 
395 	mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
396 				 clk_data);
397 
398 	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
399 				    &mt6797_clk_lock, clk_data);
400 
401 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
402 }
403 
404 static const struct mtk_gate_regs infra0_cg_regs = {
405 	.set_ofs = 0x0080,
406 	.clr_ofs = 0x0084,
407 	.sta_ofs = 0x0090,
408 };
409 
410 static const struct mtk_gate_regs infra1_cg_regs = {
411 	.set_ofs = 0x0088,
412 	.clr_ofs = 0x008c,
413 	.sta_ofs = 0x0094,
414 };
415 
416 static const struct mtk_gate_regs infra2_cg_regs = {
417 	.set_ofs = 0x00a8,
418 	.clr_ofs = 0x00ac,
419 	.sta_ofs = 0x00b0,
420 };
421 
422 #define GATE_ICG0(_id, _name, _parent, _shift) {		\
423 	.id = _id,						\
424 	.name = _name,						\
425 	.parent_name = _parent,					\
426 	.regs = &infra0_cg_regs,				\
427 	.shift = _shift,					\
428 	.ops = &mtk_clk_gate_ops_setclr,			\
429 }
430 
431 #define GATE_ICG1(_id, _name, _parent, _shift)			\
432 	GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0)
433 
434 #define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) {	\
435 	.id = _id,						\
436 	.name = _name,						\
437 	.parent_name = _parent,					\
438 	.regs = &infra1_cg_regs,				\
439 	.shift = _shift,					\
440 	.ops = &mtk_clk_gate_ops_setclr,			\
441 	.flags = _flags,					\
442 }
443 
444 #define GATE_ICG2(_id, _name, _parent, _shift)			\
445 	GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0)
446 
447 #define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) {	\
448 	.id = _id,						\
449 	.name = _name,						\
450 	.parent_name = _parent,					\
451 	.regs = &infra2_cg_regs,				\
452 	.shift = _shift,					\
453 	.ops = &mtk_clk_gate_ops_setclr,			\
454 	.flags = _flags,					\
455 }
456 
457 /*
458  * Clock gates dramc and dramc_b are needed by the DRAM controller.
459  * We mark them as critical as otherwise the system will hang after boot.
460  */
461 static const struct mtk_gate infra_clks[] = {
462 	GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0),
463 	GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1),
464 	GATE_ICG0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pmicspi_sel", 2),
465 	GATE_ICG0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pmicspi_sel", 3),
466 	GATE_ICG0(CLK_INFRA_SCP, "infra_scp", "scp_sel", 4),
467 	GATE_ICG0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
468 	GATE_ICG0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
469 	GATE_ICG0(CLK_INFRA_SEJ_13M, "infra_sej_13m", "clk26m", 7),
470 	GATE_ICG0(CLK_INFRA_ICUSB, "infra_icusb", "usb20_sel", 8),
471 	GATE_ICG0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9),
472 	GATE_ICG0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
473 	GATE_ICG0(CLK_INFRA_I2C0, "infra_i2c0", "axi_sel", 11),
474 	GATE_ICG0(CLK_INFRA_I2C1, "infra_i2c1", "axi_sel", 12),
475 	GATE_ICG0(CLK_INFRA_I2C2, "infra_i2c2", "axi_sel", 13),
476 	GATE_ICG0(CLK_INFRA_I2C3, "infra_i2c3", "axi_sel", 14),
477 	GATE_ICG0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15),
478 	GATE_ICG0(CLK_INFRA_PWM1, "infra_pwm1", "axi_sel", 16),
479 	GATE_ICG0(CLK_INFRA_PWM2, "infra_pwm2", "axi_sel", 17),
480 	GATE_ICG0(CLK_INFRA_PWM3, "infra_pwm3", "axi_sel", 18),
481 	GATE_ICG0(CLK_INFRA_PWM4, "infra_pwm4", "axi_sel", 19),
482 	GATE_ICG0(CLK_INFRA_PWM, "infra_pwm", "axi_sel", 21),
483 	GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
484 	GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
485 	GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
486 	GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
487 	GATE_ICG0(CLK_INFRA_MD2MD_CCIF_0, "infra_md2md_ccif_0", "axi_sel", 27),
488 	GATE_ICG0(CLK_INFRA_MD2MD_CCIF_1, "infra_md2md_ccif_1", "axi_sel", 28),
489 	GATE_ICG0(CLK_INFRA_MD2MD_CCIF_2, "infra_md2md_ccif_2", "axi_sel", 29),
490 	GATE_ICG0(CLK_INFRA_FHCTL, "infra_fhctl", "clk26m", 30),
491 	GATE_ICG0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
492 	GATE_ICG1(CLK_INFRA_MD2MD_CCIF_3, "infra_md2md_ccif_3", "axi_sel", 0),
493 	GATE_ICG1(CLK_INFRA_SPI, "infra_spi", "spi_sel", 1),
494 	GATE_ICG1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_sel", 2),
495 	GATE_ICG1(CLK_INFRA_MD2MD_CCIF_4, "infra_md2md_ccif_4", "axi_sel", 3),
496 	GATE_ICG1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc30_1_sel", 4),
497 	GATE_ICG1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc30_2_sel", 5),
498 	GATE_ICG1(CLK_INFRA_MD2MD_CCIF_5, "infra_md2md_ccif_5", "axi_sel", 7),
499 	GATE_ICG1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
500 	GATE_ICG1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
501 	GATE_ICG1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
502 	GATE_ICG1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
503 	GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_0, "infra_ap_c2k_ccif_0",
504 		  "axi_sel", 12),
505 	GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_1, "infra_ap_c2k_ccif_1",
506 		  "axi_sel", 13),
507 	GATE_ICG1(CLK_INFRA_CLDMA, "infra_cldma", "axi_sel", 16),
508 	GATE_ICG1(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "pwm_sel", 17),
509 	GATE_ICG1(CLK_INFRA_AP_DMA, "infra_ap_dma", "axi_sel", 18),
510 	GATE_ICG1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20),
511 	GATE_ICG1(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "mm_sel", 22),
512 	GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
513 	GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
514 	GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
515 	GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
516 			"clk26m", 31, CLK_IS_CRITICAL),
517 	GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
518 	GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
519 	GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
520 	GATE_ICG2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "axi_sel", 3),
521 	GATE_ICG2(CLK_INFRA_I2C2_ARB, "infra_i2c2_arb", "axi_sel", 4),
522 	GATE_ICG2(CLK_INFRA_I2C3_IMM, "infra_i2c3_imm", "axi_sel", 5),
523 	GATE_ICG2(CLK_INFRA_I2C3_ARB, "infra_i2c3_arb", "axi_sel", 6),
524 	GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
525 	GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
526 	GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
527 	GATE_ICG2_FLAGS(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m",
528 			"clk26m", 11, CLK_IS_CRITICAL),
529 	GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
530 	GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
531 	GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),
532 	GATE_ICG2(CLK_INFRA_AES_TOP0, "infra_aes_top0", "axi_sel", 16),
533 	GATE_ICG2(CLK_INFRA_AES_TOP1, "infra_aes_top1", "axi_sel", 17),
534 	GATE_ICG2(CLK_INFRA_SSUSB_BUS, "infra_ssusb_bus", "axi_sel", 18),
535 	GATE_ICG2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 19),
536 	GATE_ICG2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 20),
537 	GATE_ICG2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 21),
538 	GATE_ICG2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 22),
539 	GATE_ICG2(CLK_INFRA_IRTX, "infra_irtx", "spi_sel", 23),
540 	GATE_ICG2(CLK_INFRA_SSUSB_SYS, "infra_ssusb_sys",
541 		  "ssusb_top_sys_sel", 24),
542 	GATE_ICG2(CLK_INFRA_SSUSB_REF, "infra_ssusb_ref", "clk26m", 9),
543 	GATE_ICG2(CLK_INFRA_AUDIO_26M, "infra_audio_26m", "clk26m", 26),
544 	GATE_ICG2(CLK_INFRA_AUDIO_26M_PAD_TOP, "infra_audio_26m_pad_top",
545 		  "clk26m", 27),
546 	GATE_ICG2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share",
547 		  "axi_sel", 28),
548 	GATE_ICG2(CLK_INFRA_VAD_WRAP_SOC, "infra_vad_wrap_soc", "axi_sel", 29),
549 	GATE_ICG2(CLK_INFRA_DRAMC_CONF, "infra_dramc_conf", "axi_sel", 30),
550 	GATE_ICG2(CLK_INFRA_DRAMC_B_CONF, "infra_dramc_b_conf", "axi_sel", 31),
551 	GATE_ICG1(CLK_INFRA_MFG_VCG, "infra_mfg_vcg", "mfg_52m_sel", 14),
552 };
553 
554 static const struct mtk_fixed_factor infra_fixed_divs[] = {
555 	FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2),
556 };
557 
558 static struct clk_onecell_data *infra_clk_data;
559 
560 static void mtk_infrasys_init_early(struct device_node *node)
561 {
562 	int r, i;
563 
564 	if (!infra_clk_data) {
565 		infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
566 
567 		for (i = 0; i < CLK_INFRA_NR; i++)
568 			infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
569 	}
570 
571 	mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
572 				 infra_clk_data);
573 
574 	r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
575 	if (r)
576 		pr_err("%s(): could not register clock provider: %d\n",
577 		       __func__, r);
578 }
579 
580 CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg",
581 		      mtk_infrasys_init_early);
582 
583 static int mtk_infrasys_init(struct platform_device *pdev)
584 {
585 	int r, i;
586 	struct device_node *node = pdev->dev.of_node;
587 
588 	if (!infra_clk_data) {
589 		infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
590 	} else {
591 		for (i = 0; i < CLK_INFRA_NR; i++) {
592 			if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
593 				infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
594 		}
595 	}
596 
597 	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
598 			       infra_clk_data);
599 	mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
600 				 infra_clk_data);
601 
602 	r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
603 	if (r)
604 		return r;
605 
606 	return 0;
607 }
608 
609 #define MT6797_PLL_FMAX		(3000UL * MHZ)
610 
611 #define CON0_MT6797_RST_BAR	BIT(24)
612 
613 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
614 			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
615 			_pcw_shift, _div_table) {			\
616 	.id = _id,						\
617 	.name = _name,						\
618 	.reg = _reg,						\
619 	.pwr_reg = _pwr_reg,					\
620 	.en_mask = _en_mask,					\
621 	.flags = _flags,					\
622 	.rst_bar_mask = CON0_MT6797_RST_BAR,			\
623 	.fmax = MT6797_PLL_FMAX,				\
624 	.pcwbits = _pcwbits,					\
625 	.pd_reg = _pd_reg,					\
626 	.pd_shift = _pd_shift,					\
627 	.tuner_reg = _tuner_reg,				\
628 	.pcw_reg = _pcw_reg,					\
629 	.pcw_shift = _pcw_shift,				\
630 	.div_table = _div_table,				\
631 }
632 
633 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
634 			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
635 			_pcw_shift)					\
636 		PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
637 			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
638 			NULL)
639 
640 static const struct mtk_pll_data plls[] = {
641 	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000101, PLL_AO,
642 	    21, 0x220, 4, 0x0, 0x224, 0),
643 	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000011, 0, 7,
644 	    0x230, 4, 0x0, 0x234, 14),
645 	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000101, 0, 21,
646 	    0x244, 24, 0x0, 0x244, 0),
647 	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000121, 0, 21,
648 	    0x250, 4, 0x0, 0x254, 0),
649 	PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000121, 0, 21,
650 	    0x260, 4, 0x0, 0x264, 0),
651 	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000121, 0, 21,
652 	    0x270, 4, 0x0, 0x274, 0),
653 	PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000121, 0, 21,
654 	    0x290, 4, 0x0, 0x294, 0),
655 	PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000121, 0, 21,
656 	    0x2E4, 4, 0x0, 0x2E8, 0),
657 	PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000131, 0, 31,
658 	    0x2A0, 4, 0x2A8, 0x2A4, 0),
659 	PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000131, 0, 31,
660 	    0x2B4, 4, 0x2BC, 0x2B8, 0),
661 };
662 
663 static int mtk_apmixedsys_init(struct platform_device *pdev)
664 {
665 	struct clk_onecell_data *clk_data;
666 	struct device_node *node = pdev->dev.of_node;
667 
668 	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
669 	if (!clk_data)
670 		return -ENOMEM;
671 
672 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
673 
674 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
675 }
676 
677 static const struct of_device_id of_match_clk_mt6797[] = {
678 	{
679 		.compatible = "mediatek,mt6797-topckgen",
680 		.data = mtk_topckgen_init,
681 	}, {
682 		.compatible = "mediatek,mt6797-infracfg",
683 		.data = mtk_infrasys_init,
684 	}, {
685 		.compatible = "mediatek,mt6797-apmixedsys",
686 		.data = mtk_apmixedsys_init,
687 	}, {
688 		/* sentinel */
689 	}
690 };
691 
692 static int clk_mt6797_probe(struct platform_device *pdev)
693 {
694 	int (*clk_init)(struct platform_device *);
695 	int r;
696 
697 	clk_init = of_device_get_match_data(&pdev->dev);
698 	if (!clk_init)
699 		return -EINVAL;
700 
701 	r = clk_init(pdev);
702 	if (r)
703 		dev_err(&pdev->dev,
704 			"could not register clock provider: %s: %d\n",
705 			pdev->name, r);
706 
707 	return r;
708 }
709 
710 static struct platform_driver clk_mt6797_drv = {
711 	.probe = clk_mt6797_probe,
712 	.driver = {
713 		.name = "clk-mt6797",
714 		.of_match_table = of_match_clk_mt6797,
715 	},
716 };
717 
718 static int __init clk_mt6797_init(void)
719 {
720 	return platform_driver_register(&clk_mt6797_drv);
721 }
722 
723 arch_initcall(clk_mt6797_init);
724