11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 296596aa0SKevin-CW Chen /* 396596aa0SKevin-CW Chen * Copyright (c) 2016 MediaTek Inc. 496596aa0SKevin-CW Chen * Author: Kevin Chen <kevin-cw.chen@mediatek.com> 596596aa0SKevin-CW Chen */ 696596aa0SKevin-CW Chen 796596aa0SKevin-CW Chen #include <linux/of.h> 896596aa0SKevin-CW Chen #include <linux/of_address.h> 996596aa0SKevin-CW Chen #include <linux/of_device.h> 1096596aa0SKevin-CW Chen #include <linux/platform_device.h> 1196596aa0SKevin-CW Chen 1296596aa0SKevin-CW Chen #include "clk-mtk.h" 1396596aa0SKevin-CW Chen #include "clk-gate.h" 1496596aa0SKevin-CW Chen 1596596aa0SKevin-CW Chen #include <dt-bindings/clock/mt6797-clk.h> 1696596aa0SKevin-CW Chen 1796596aa0SKevin-CW Chen /* 1896596aa0SKevin-CW Chen * For some clocks, we don't care what their actual rates are. And these 1996596aa0SKevin-CW Chen * clocks may change their rate on different products or different scenarios. 2096596aa0SKevin-CW Chen * So we model these clocks' rate as 0, to denote it's not an actual rate. 2196596aa0SKevin-CW Chen */ 2296596aa0SKevin-CW Chen 2396596aa0SKevin-CW Chen static DEFINE_SPINLOCK(mt6797_clk_lock); 2496596aa0SKevin-CW Chen 2596596aa0SKevin-CW Chen static const struct mtk_fixed_factor top_fixed_divs[] = { 2696596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1), 2796596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 2896596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2), 2996596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4), 3096596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8), 3196596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16), 3296596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3), 3396596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL_D3_D3, "syspll_d3_d3", "syspll_d3", 1, 3), 3496596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2), 3596596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4), 3696596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8), 3796596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 3896596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2), 3996596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4), 4096596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), 4196596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2), 4296596aa0SKevin-CW Chen FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4), 4396596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1), 4496596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 4596596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26), 4696596aa0SKevin-CW Chen FACTOR(CLK_TOP_SSUSB_PHY_48M_CK, "ssusb_phy_48m_ck", "univpll", 1, 1), 4796596aa0SKevin-CW Chen FACTOR(CLK_TOP_USB_PHY48M_CK, "usb_phy48m_ck", "univpll", 1, 1), 4896596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 4996596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2), 5096596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4), 5196596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8), 5296596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 5396596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 2), 5496596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4), 5596596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8), 5696596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 5796596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2), 5896596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4), 5996596aa0SKevin-CW Chen FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8), 6096596aa0SKevin-CW Chen FACTOR(CLK_TOP_ULPOSC_CK_ORG, "ulposc_ck_org", "ulposc", 1, 1), 6196596aa0SKevin-CW Chen FACTOR(CLK_TOP_ULPOSC_CK, "ulposc_ck", "ulposc_ck_org", 1, 3), 6296596aa0SKevin-CW Chen FACTOR(CLK_TOP_ULPOSC_D2, "ulposc_d2", "ulposc_ck", 1, 2), 6396596aa0SKevin-CW Chen FACTOR(CLK_TOP_ULPOSC_D3, "ulposc_d3", "ulposc_ck", 1, 4), 6496596aa0SKevin-CW Chen FACTOR(CLK_TOP_ULPOSC_D4, "ulposc_d4", "ulposc_ck", 1, 8), 6596596aa0SKevin-CW Chen FACTOR(CLK_TOP_ULPOSC_D8, "ulposc_d8", "ulposc_ck", 1, 10), 6696596aa0SKevin-CW Chen FACTOR(CLK_TOP_ULPOSC_D10, "ulposc_d10", "ulposc_ck_org", 1, 1), 6796596aa0SKevin-CW Chen FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1), 6896596aa0SKevin-CW Chen FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1), 6996596aa0SKevin-CW Chen FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1), 7096596aa0SKevin-CW Chen FACTOR(CLK_TOP_MFGPLL_D2, "mfgpll_d2", "mfgpll_ck", 1, 2), 7196596aa0SKevin-CW Chen FACTOR(CLK_TOP_IMGPLL_CK, "imgpll_ck", "imgpll", 1, 1), 7296596aa0SKevin-CW Chen FACTOR(CLK_TOP_IMGPLL_D2, "imgpll_d2", "imgpll_ck", 1, 2), 7396596aa0SKevin-CW Chen FACTOR(CLK_TOP_IMGPLL_D4, "imgpll_d4", "imgpll_ck", 1, 4), 7496596aa0SKevin-CW Chen FACTOR(CLK_TOP_CODECPLL_CK, "codecpll_ck", "codecpll", 1, 1), 7596596aa0SKevin-CW Chen FACTOR(CLK_TOP_CODECPLL_D2, "codecpll_d2", "codecpll_ck", 1, 2), 7696596aa0SKevin-CW Chen FACTOR(CLK_TOP_VDECPLL_CK, "vdecpll_ck", "vdecpll", 1, 1), 7796596aa0SKevin-CW Chen FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1), 7896596aa0SKevin-CW Chen FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), 7996596aa0SKevin-CW Chen FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4), 8096596aa0SKevin-CW Chen FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8), 8196596aa0SKevin-CW Chen FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16), 8296596aa0SKevin-CW Chen FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1), 8396596aa0SKevin-CW Chen FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2), 8496596aa0SKevin-CW Chen FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4), 8596596aa0SKevin-CW Chen FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll_ck", 1, 8), 8696596aa0SKevin-CW Chen }; 8796596aa0SKevin-CW Chen 8896596aa0SKevin-CW Chen static const char * const axi_parents[] = { 8996596aa0SKevin-CW Chen "clk26m", 9096596aa0SKevin-CW Chen "syspll_d7", 9196596aa0SKevin-CW Chen "ulposc_axi_ck_mux", 9296596aa0SKevin-CW Chen }; 9396596aa0SKevin-CW Chen 9496596aa0SKevin-CW Chen static const char * const ulposc_axi_ck_mux_parents[] = { 9596596aa0SKevin-CW Chen "syspll1_d4", 9696596aa0SKevin-CW Chen "ulposc_axi_ck_mux_pre", 9796596aa0SKevin-CW Chen }; 9896596aa0SKevin-CW Chen 9996596aa0SKevin-CW Chen static const char * const ulposc_axi_ck_mux_pre_parents[] = { 10096596aa0SKevin-CW Chen "ulposc_d2", 10196596aa0SKevin-CW Chen "ulposc_d3", 10296596aa0SKevin-CW Chen }; 10396596aa0SKevin-CW Chen 10496596aa0SKevin-CW Chen static const char * const ddrphycfg_parents[] = { 10596596aa0SKevin-CW Chen "clk26m", 10696596aa0SKevin-CW Chen "syspll3_d2", 10796596aa0SKevin-CW Chen "syspll2_d4", 10896596aa0SKevin-CW Chen "syspll1_d8", 10996596aa0SKevin-CW Chen }; 11096596aa0SKevin-CW Chen 11196596aa0SKevin-CW Chen static const char * const mm_parents[] = { 11296596aa0SKevin-CW Chen "clk26m", 11396596aa0SKevin-CW Chen "imgpll_ck", 11496596aa0SKevin-CW Chen "univpll1_d2", 11596596aa0SKevin-CW Chen "syspll1_d2", 11696596aa0SKevin-CW Chen }; 11796596aa0SKevin-CW Chen 11896596aa0SKevin-CW Chen static const char * const pwm_parents[] = { 11996596aa0SKevin-CW Chen "clk26m", 12096596aa0SKevin-CW Chen "univpll2_d4", 12196596aa0SKevin-CW Chen "ulposc_d2", 12296596aa0SKevin-CW Chen "ulposc_d3", 12396596aa0SKevin-CW Chen "ulposc_d8", 12496596aa0SKevin-CW Chen "ulposc_d10", 12596596aa0SKevin-CW Chen "ulposc_d4", 12696596aa0SKevin-CW Chen }; 12796596aa0SKevin-CW Chen 12896596aa0SKevin-CW Chen static const char * const vdec_parents[] = { 12996596aa0SKevin-CW Chen "clk26m", 13096596aa0SKevin-CW Chen "vdecpll_ck", 13196596aa0SKevin-CW Chen "imgpll_ck", 13296596aa0SKevin-CW Chen "syspll_d3", 13396596aa0SKevin-CW Chen "univpll_d5", 13496596aa0SKevin-CW Chen "clk26m", 13596596aa0SKevin-CW Chen "clk26m", 13696596aa0SKevin-CW Chen }; 13796596aa0SKevin-CW Chen 13896596aa0SKevin-CW Chen static const char * const venc_parents[] = { 13996596aa0SKevin-CW Chen "clk26m", 14096596aa0SKevin-CW Chen "codecpll_ck", 14196596aa0SKevin-CW Chen "syspll_d3", 14296596aa0SKevin-CW Chen }; 14396596aa0SKevin-CW Chen 14496596aa0SKevin-CW Chen static const char * const mfg_parents[] = { 14596596aa0SKevin-CW Chen "clk26m", 14696596aa0SKevin-CW Chen "mfgpll_ck", 14796596aa0SKevin-CW Chen "syspll_d3", 14896596aa0SKevin-CW Chen "univpll_d3", 14996596aa0SKevin-CW Chen }; 15096596aa0SKevin-CW Chen 15196596aa0SKevin-CW Chen static const char * const camtg[] = { 15296596aa0SKevin-CW Chen "clk26m", 15396596aa0SKevin-CW Chen "univpll_d26", 15496596aa0SKevin-CW Chen "univpll2_d2", 15596596aa0SKevin-CW Chen }; 15696596aa0SKevin-CW Chen 15796596aa0SKevin-CW Chen static const char * const uart_parents[] = { 15896596aa0SKevin-CW Chen "clk26m", 15996596aa0SKevin-CW Chen "univpll2_d8", 16096596aa0SKevin-CW Chen }; 16196596aa0SKevin-CW Chen 16296596aa0SKevin-CW Chen static const char * const spi_parents[] = { 16396596aa0SKevin-CW Chen "clk26m", 16496596aa0SKevin-CW Chen "syspll3_d2", 16596596aa0SKevin-CW Chen "syspll2_d4", 16696596aa0SKevin-CW Chen "ulposc_spi_ck_mux", 16796596aa0SKevin-CW Chen }; 16896596aa0SKevin-CW Chen 16996596aa0SKevin-CW Chen static const char * const ulposc_spi_ck_mux_parents[] = { 17096596aa0SKevin-CW Chen "ulposc_d2", 17196596aa0SKevin-CW Chen "ulposc_d3", 17296596aa0SKevin-CW Chen }; 17396596aa0SKevin-CW Chen 17496596aa0SKevin-CW Chen static const char * const usb20_parents[] = { 17596596aa0SKevin-CW Chen "clk26m", 17696596aa0SKevin-CW Chen "univpll1_d8", 17796596aa0SKevin-CW Chen "syspll4_d2", 17896596aa0SKevin-CW Chen }; 17996596aa0SKevin-CW Chen 18096596aa0SKevin-CW Chen static const char * const msdc50_0_hclk_parents[] = { 18196596aa0SKevin-CW Chen "clk26m", 18296596aa0SKevin-CW Chen "syspll1_d2", 18396596aa0SKevin-CW Chen "syspll2_d2", 18496596aa0SKevin-CW Chen "syspll4_d2", 18596596aa0SKevin-CW Chen }; 18696596aa0SKevin-CW Chen 18796596aa0SKevin-CW Chen static const char * const msdc50_0_parents[] = { 18896596aa0SKevin-CW Chen "clk26m", 18996596aa0SKevin-CW Chen "msdcpll", 19096596aa0SKevin-CW Chen "syspll_d3", 19196596aa0SKevin-CW Chen "univpll1_d4", 19296596aa0SKevin-CW Chen "syspll2_d2", 19396596aa0SKevin-CW Chen "syspll_d7", 19496596aa0SKevin-CW Chen "msdcpll_d2", 19596596aa0SKevin-CW Chen "univpll1_d2", 19696596aa0SKevin-CW Chen "univpll_d3", 19796596aa0SKevin-CW Chen }; 19896596aa0SKevin-CW Chen 19996596aa0SKevin-CW Chen static const char * const msdc30_1_parents[] = { 20096596aa0SKevin-CW Chen "clk26m", 20196596aa0SKevin-CW Chen "univpll2_d2", 20296596aa0SKevin-CW Chen "msdcpll_d2", 20396596aa0SKevin-CW Chen "univpll1_d4", 20496596aa0SKevin-CW Chen "syspll2_d2", 20596596aa0SKevin-CW Chen "syspll_d7", 20696596aa0SKevin-CW Chen "univpll_d7", 20796596aa0SKevin-CW Chen }; 20896596aa0SKevin-CW Chen 20996596aa0SKevin-CW Chen static const char * const msdc30_2_parents[] = { 21096596aa0SKevin-CW Chen "clk26m", 21196596aa0SKevin-CW Chen "univpll2_d8", 21296596aa0SKevin-CW Chen "syspll2_d8", 21396596aa0SKevin-CW Chen "syspll1_d8", 21496596aa0SKevin-CW Chen "msdcpll_d8", 21596596aa0SKevin-CW Chen "syspll3_d4", 21696596aa0SKevin-CW Chen "univpll_d26", 21796596aa0SKevin-CW Chen }; 21896596aa0SKevin-CW Chen 21996596aa0SKevin-CW Chen static const char * const audio_parents[] = { 22096596aa0SKevin-CW Chen "clk26m", 22196596aa0SKevin-CW Chen "syspll3_d4", 22296596aa0SKevin-CW Chen "syspll4_d4", 22396596aa0SKevin-CW Chen "syspll1_d16", 22496596aa0SKevin-CW Chen }; 22596596aa0SKevin-CW Chen 22696596aa0SKevin-CW Chen static const char * const aud_intbus_parents[] = { 22796596aa0SKevin-CW Chen "clk26m", 22896596aa0SKevin-CW Chen "syspll1_d4", 22996596aa0SKevin-CW Chen "syspll4_d2", 23096596aa0SKevin-CW Chen }; 23196596aa0SKevin-CW Chen 23296596aa0SKevin-CW Chen static const char * const pmicspi_parents[] = { 23396596aa0SKevin-CW Chen "clk26m", 23496596aa0SKevin-CW Chen "univpll_d26", 23596596aa0SKevin-CW Chen "syspll3_d4", 23696596aa0SKevin-CW Chen "syspll1_d8", 23796596aa0SKevin-CW Chen "ulposc_d4", 23896596aa0SKevin-CW Chen "ulposc_d8", 23996596aa0SKevin-CW Chen "syspll2_d8", 24096596aa0SKevin-CW Chen }; 24196596aa0SKevin-CW Chen 24296596aa0SKevin-CW Chen static const char * const scp_parents[] = { 24396596aa0SKevin-CW Chen "clk26m", 24496596aa0SKevin-CW Chen "syspll_d3", 24596596aa0SKevin-CW Chen "ulposc_ck", 24696596aa0SKevin-CW Chen "univpll_d5", 24796596aa0SKevin-CW Chen }; 24896596aa0SKevin-CW Chen 24996596aa0SKevin-CW Chen static const char * const atb_parents[] = { 25096596aa0SKevin-CW Chen "clk26m", 25196596aa0SKevin-CW Chen "syspll1_d2", 25296596aa0SKevin-CW Chen "syspll_d5", 25396596aa0SKevin-CW Chen }; 25496596aa0SKevin-CW Chen 25596596aa0SKevin-CW Chen static const char * const mjc_parents[] = { 25696596aa0SKevin-CW Chen "clk26m", 25796596aa0SKevin-CW Chen "imgpll_ck", 25896596aa0SKevin-CW Chen "univpll_d5", 25996596aa0SKevin-CW Chen "syspll1_d2", 26096596aa0SKevin-CW Chen }; 26196596aa0SKevin-CW Chen 26296596aa0SKevin-CW Chen static const char * const dpi0_parents[] = { 26396596aa0SKevin-CW Chen "clk26m", 26496596aa0SKevin-CW Chen "tvdpll_d2", 26596596aa0SKevin-CW Chen "tvdpll_d4", 26696596aa0SKevin-CW Chen "tvdpll_d8", 26796596aa0SKevin-CW Chen "tvdpll_d16", 26896596aa0SKevin-CW Chen "clk26m", 26996596aa0SKevin-CW Chen "clk26m", 27096596aa0SKevin-CW Chen }; 27196596aa0SKevin-CW Chen 27296596aa0SKevin-CW Chen static const char * const aud_1_parents[] = { 27396596aa0SKevin-CW Chen "clk26m", 27496596aa0SKevin-CW Chen "apll1_ck", 27596596aa0SKevin-CW Chen }; 27696596aa0SKevin-CW Chen 27796596aa0SKevin-CW Chen static const char * const aud_2_parents[] = { 27896596aa0SKevin-CW Chen "clk26m", 27996596aa0SKevin-CW Chen "apll2_ck", 28096596aa0SKevin-CW Chen }; 28196596aa0SKevin-CW Chen 28296596aa0SKevin-CW Chen static const char * const ssusb_top_sys_parents[] = { 28396596aa0SKevin-CW Chen "clk26m", 28496596aa0SKevin-CW Chen "univpll3_d2", 28596596aa0SKevin-CW Chen }; 28696596aa0SKevin-CW Chen 28796596aa0SKevin-CW Chen static const char * const spm_parents[] = { 28896596aa0SKevin-CW Chen "clk26m", 28996596aa0SKevin-CW Chen "syspll1_d8", 29096596aa0SKevin-CW Chen }; 29196596aa0SKevin-CW Chen 29296596aa0SKevin-CW Chen static const char * const bsi_spi_parents[] = { 29396596aa0SKevin-CW Chen "clk26m", 29496596aa0SKevin-CW Chen "syspll_d3_d3", 29596596aa0SKevin-CW Chen "syspll1_d4", 29696596aa0SKevin-CW Chen "syspll_d7", 29796596aa0SKevin-CW Chen }; 29896596aa0SKevin-CW Chen 29996596aa0SKevin-CW Chen static const char * const audio_h_parents[] = { 30096596aa0SKevin-CW Chen "clk26m", 30196596aa0SKevin-CW Chen "apll2_ck", 30296596aa0SKevin-CW Chen "apll1_ck", 30396596aa0SKevin-CW Chen "univpll_d7", 30496596aa0SKevin-CW Chen }; 30596596aa0SKevin-CW Chen 30696596aa0SKevin-CW Chen static const char * const mfg_52m_parents[] = { 30796596aa0SKevin-CW Chen "clk26m", 30896596aa0SKevin-CW Chen "univpll2_d8", 30996596aa0SKevin-CW Chen "univpll2_d4", 31096596aa0SKevin-CW Chen "univpll2_d4", 31196596aa0SKevin-CW Chen }; 31296596aa0SKevin-CW Chen 31396596aa0SKevin-CW Chen static const char * const anc_md32_parents[] = { 31496596aa0SKevin-CW Chen "clk26m", 31596596aa0SKevin-CW Chen "syspll1_d2", 31696596aa0SKevin-CW Chen "univpll_d5", 31796596aa0SKevin-CW Chen }; 31896596aa0SKevin-CW Chen 319b35656deSJasper Mattsson /* 320b35656deSJasper Mattsson * Clock mux ddrphycfg is needed by the DRAM controller. We mark it as 321b35656deSJasper Mattsson * critical as otherwise the system will hang after boot. 322b35656deSJasper Mattsson */ 32396596aa0SKevin-CW Chen static const struct mtk_composite top_muxes[] = { 32496596aa0SKevin-CW Chen MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre", 32596596aa0SKevin-CW Chen ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1), 32696596aa0SKevin-CW Chen MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux", 32796596aa0SKevin-CW Chen ulposc_axi_ck_mux_parents, 0x0040, 2, 1), 32896596aa0SKevin-CW Chen MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents, 32996596aa0SKevin-CW Chen 0x0040, 0, 2), 330b35656deSJasper Mattsson MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents, 331b35656deSJasper Mattsson 0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 33296596aa0SKevin-CW Chen MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents, 33396596aa0SKevin-CW Chen 0x0040, 24, 2), 33496596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7), 33596596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_VDEC, "vdec_sel", vdec_parents, 0x0050, 8, 3, 15), 33696596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_VENC, "venc_sel", venc_parents, 0x0050, 16, 2, 23), 33796596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_MFG, "mfg_sel", mfg_parents, 0x0050, 24, 2, 31), 33896596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg, 0x0060, 0, 2, 7), 33996596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15), 34096596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, 0x0060, 16, 2, 23), 34196596aa0SKevin-CW Chen MUX(CLK_TOP_MUX_ULPOSC_SPI_CK_MUX, "ulposc_spi_ck_mux", 34296596aa0SKevin-CW Chen ulposc_spi_ck_mux_parents, 0x0060, 18, 1), 34396596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents, 34496596aa0SKevin-CW Chen 0x0060, 24, 2, 31), 34596596aa0SKevin-CW Chen MUX(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel", 34696596aa0SKevin-CW Chen msdc50_0_hclk_parents, 0x0070, 8, 2), 34796596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents, 34896596aa0SKevin-CW Chen 0x0070, 16, 4, 23), 34996596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents, 35096596aa0SKevin-CW Chen 0x0070, 24, 3, 31), 35196596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", msdc30_2_parents, 35296596aa0SKevin-CW Chen 0x0080, 0, 3, 7), 35396596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_AUDIO, "audio_sel", audio_parents, 35496596aa0SKevin-CW Chen 0x0080, 16, 2, 23), 35596596aa0SKevin-CW Chen MUX(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", aud_intbus_parents, 35696596aa0SKevin-CW Chen 0x0080, 24, 2), 35796596aa0SKevin-CW Chen MUX(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents, 35896596aa0SKevin-CW Chen 0x0090, 0, 3), 35996596aa0SKevin-CW Chen MUX(CLK_TOP_MUX_SCP, "scp_sel", scp_parents, 36096596aa0SKevin-CW Chen 0x0090, 8, 2), 36196596aa0SKevin-CW Chen MUX(CLK_TOP_MUX_ATB, "atb_sel", atb_parents, 36296596aa0SKevin-CW Chen 0x0090, 16, 2), 36396596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_MJC, "mjc_sel", mjc_parents, 0x0090, 24, 2, 31), 36496596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_DPI0, "dpi0_sel", dpi0_parents, 0x00A0, 0, 3, 7), 36596596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents, 36696596aa0SKevin-CW Chen 0x00A0, 16, 1, 23), 36796596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents, 36896596aa0SKevin-CW Chen 0x00A0, 24, 1, 31), 36996596aa0SKevin-CW Chen MUX(CLK_TOP_MUX_SSUSB_TOP_SYS, "ssusb_top_sys_sel", 37096596aa0SKevin-CW Chen ssusb_top_sys_parents, 0x00B0, 8, 1), 37196596aa0SKevin-CW Chen MUX(CLK_TOP_MUX_SPM, "spm_sel", spm_parents, 37296596aa0SKevin-CW Chen 0x00C0, 0, 1), 37396596aa0SKevin-CW Chen MUX(CLK_TOP_MUX_BSI_SPI, "bsi_spi_sel", bsi_spi_parents, 37496596aa0SKevin-CW Chen 0x00C0, 8, 2), 37596596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_AUDIO_H, "audio_h_sel", audio_h_parents, 37696596aa0SKevin-CW Chen 0x00C0, 16, 2, 23), 37796596aa0SKevin-CW Chen MUX_GATE(CLK_TOP_MUX_ANC_MD32, "anc_md32_sel", anc_md32_parents, 37896596aa0SKevin-CW Chen 0x00C0, 24, 2, 31), 37996596aa0SKevin-CW Chen MUX(CLK_TOP_MUX_MFG_52M, "mfg_52m_sel", mfg_52m_parents, 38096596aa0SKevin-CW Chen 0x0104, 1, 2), 38196596aa0SKevin-CW Chen }; 38296596aa0SKevin-CW Chen 38396596aa0SKevin-CW Chen static int mtk_topckgen_init(struct platform_device *pdev) 38496596aa0SKevin-CW Chen { 38596596aa0SKevin-CW Chen struct clk_onecell_data *clk_data; 38696596aa0SKevin-CW Chen void __iomem *base; 38796596aa0SKevin-CW Chen struct device_node *node = pdev->dev.of_node; 38896596aa0SKevin-CW Chen struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 38996596aa0SKevin-CW Chen 39096596aa0SKevin-CW Chen base = devm_ioremap_resource(&pdev->dev, res); 39196596aa0SKevin-CW Chen if (IS_ERR(base)) 39296596aa0SKevin-CW Chen return PTR_ERR(base); 39396596aa0SKevin-CW Chen 39496596aa0SKevin-CW Chen clk_data = mtk_alloc_clk_data(CLK_TOP_NR); 39596596aa0SKevin-CW Chen 39696596aa0SKevin-CW Chen mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), 39796596aa0SKevin-CW Chen clk_data); 39896596aa0SKevin-CW Chen 39996596aa0SKevin-CW Chen mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, 40096596aa0SKevin-CW Chen &mt6797_clk_lock, clk_data); 40196596aa0SKevin-CW Chen 40296596aa0SKevin-CW Chen return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 40396596aa0SKevin-CW Chen } 40496596aa0SKevin-CW Chen 40596596aa0SKevin-CW Chen static const struct mtk_gate_regs infra0_cg_regs = { 40696596aa0SKevin-CW Chen .set_ofs = 0x0080, 40796596aa0SKevin-CW Chen .clr_ofs = 0x0084, 40896596aa0SKevin-CW Chen .sta_ofs = 0x0090, 40996596aa0SKevin-CW Chen }; 41096596aa0SKevin-CW Chen 41196596aa0SKevin-CW Chen static const struct mtk_gate_regs infra1_cg_regs = { 41296596aa0SKevin-CW Chen .set_ofs = 0x0088, 41396596aa0SKevin-CW Chen .clr_ofs = 0x008c, 41496596aa0SKevin-CW Chen .sta_ofs = 0x0094, 41596596aa0SKevin-CW Chen }; 41696596aa0SKevin-CW Chen 41796596aa0SKevin-CW Chen static const struct mtk_gate_regs infra2_cg_regs = { 41896596aa0SKevin-CW Chen .set_ofs = 0x00a8, 41996596aa0SKevin-CW Chen .clr_ofs = 0x00ac, 42096596aa0SKevin-CW Chen .sta_ofs = 0x00b0, 42196596aa0SKevin-CW Chen }; 42296596aa0SKevin-CW Chen 42396596aa0SKevin-CW Chen #define GATE_ICG0(_id, _name, _parent, _shift) { \ 42496596aa0SKevin-CW Chen .id = _id, \ 42596596aa0SKevin-CW Chen .name = _name, \ 42696596aa0SKevin-CW Chen .parent_name = _parent, \ 42796596aa0SKevin-CW Chen .regs = &infra0_cg_regs, \ 42896596aa0SKevin-CW Chen .shift = _shift, \ 42996596aa0SKevin-CW Chen .ops = &mtk_clk_gate_ops_setclr, \ 43096596aa0SKevin-CW Chen } 43196596aa0SKevin-CW Chen 432b35656deSJasper Mattsson #define GATE_ICG1(_id, _name, _parent, _shift) \ 433b35656deSJasper Mattsson GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0) 434b35656deSJasper Mattsson 435b35656deSJasper Mattsson #define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \ 43696596aa0SKevin-CW Chen .id = _id, \ 43796596aa0SKevin-CW Chen .name = _name, \ 43896596aa0SKevin-CW Chen .parent_name = _parent, \ 43996596aa0SKevin-CW Chen .regs = &infra1_cg_regs, \ 44096596aa0SKevin-CW Chen .shift = _shift, \ 44196596aa0SKevin-CW Chen .ops = &mtk_clk_gate_ops_setclr, \ 442b35656deSJasper Mattsson .flags = _flags, \ 44396596aa0SKevin-CW Chen } 44496596aa0SKevin-CW Chen 445b35656deSJasper Mattsson #define GATE_ICG2(_id, _name, _parent, _shift) \ 446b35656deSJasper Mattsson GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0) 447b35656deSJasper Mattsson 448b35656deSJasper Mattsson #define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \ 44996596aa0SKevin-CW Chen .id = _id, \ 45096596aa0SKevin-CW Chen .name = _name, \ 45196596aa0SKevin-CW Chen .parent_name = _parent, \ 45296596aa0SKevin-CW Chen .regs = &infra2_cg_regs, \ 45396596aa0SKevin-CW Chen .shift = _shift, \ 45496596aa0SKevin-CW Chen .ops = &mtk_clk_gate_ops_setclr, \ 455b35656deSJasper Mattsson .flags = _flags, \ 45696596aa0SKevin-CW Chen } 45796596aa0SKevin-CW Chen 458b35656deSJasper Mattsson /* 459b35656deSJasper Mattsson * Clock gates dramc and dramc_b are needed by the DRAM controller. 460b35656deSJasper Mattsson * We mark them as critical as otherwise the system will hang after boot. 461b35656deSJasper Mattsson */ 46296596aa0SKevin-CW Chen static const struct mtk_gate infra_clks[] = { 46396596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0), 46496596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1), 46596596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pmicspi_sel", 2), 46696596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pmicspi_sel", 3), 46796596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_SCP, "infra_scp", "scp_sel", 4), 46896596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5), 46996596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6), 47096596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_SEJ_13M, "infra_sej_13m", "clk26m", 7), 47196596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_ICUSB, "infra_icusb", "usb20_sel", 8), 47296596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9), 47396596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10), 47496596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_I2C0, "infra_i2c0", "axi_sel", 11), 47596596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_I2C1, "infra_i2c1", "axi_sel", 12), 47696596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_I2C2, "infra_i2c2", "axi_sel", 13), 47796596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_I2C3, "infra_i2c3", "axi_sel", 14), 47896596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15), 47996596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_PWM1, "infra_pwm1", "axi_sel", 16), 48096596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_PWM2, "infra_pwm2", "axi_sel", 17), 48196596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_PWM3, "infra_pwm3", "axi_sel", 18), 48296596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_PWM4, "infra_pwm4", "axi_sel", 19), 48396596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_PWM, "infra_pwm", "axi_sel", 21), 48496596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22), 48596596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), 48696596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), 48796596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25), 48896596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_MD2MD_CCIF_0, "infra_md2md_ccif_0", "axi_sel", 27), 48996596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_MD2MD_CCIF_1, "infra_md2md_ccif_1", "axi_sel", 28), 49096596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_MD2MD_CCIF_2, "infra_md2md_ccif_2", "axi_sel", 29), 49196596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_FHCTL, "infra_fhctl", "clk26m", 30), 49296596aa0SKevin-CW Chen GATE_ICG0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31), 49396596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_MD2MD_CCIF_3, "infra_md2md_ccif_3", "axi_sel", 0), 49496596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_SPI, "infra_spi", "spi_sel", 1), 49596596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_sel", 2), 49696596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_MD2MD_CCIF_4, "infra_md2md_ccif_4", "axi_sel", 3), 49796596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc30_1_sel", 4), 49896596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc30_2_sel", 5), 49996596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_MD2MD_CCIF_5, "infra_md2md_ccif_5", "axi_sel", 7), 50096596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8), 50196596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9), 50296596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10), 50396596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11), 50496596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_0, "infra_ap_c2k_ccif_0", 50596596aa0SKevin-CW Chen "axi_sel", 12), 50696596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_1, "infra_ap_c2k_ccif_1", 50796596aa0SKevin-CW Chen "axi_sel", 13), 50896596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_CLDMA, "infra_cldma", "axi_sel", 16), 50996596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "pwm_sel", 17), 51096596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_AP_DMA, "infra_ap_dma", "axi_sel", 18), 51196596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20), 51296596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "mm_sel", 22), 51396596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23), 51496596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25), 51596596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26), 516b35656deSJasper Mattsson GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", 517b35656deSJasper Mattsson "clk26m", 31, CLK_IS_CRITICAL), 51896596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0), 51996596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1), 52096596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2), 52196596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "axi_sel", 3), 52296596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_I2C2_ARB, "infra_i2c2_arb", "axi_sel", 4), 52396596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_I2C3_IMM, "infra_i2c3_imm", "axi_sel", 5), 52496596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_I2C3_ARB, "infra_i2c3_arb", "axi_sel", 6), 52596596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7), 52696596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8), 52796596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10), 528b35656deSJasper Mattsson GATE_ICG2_FLAGS(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m", 529b35656deSJasper Mattsson "clk26m", 11, CLK_IS_CRITICAL), 53096596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12), 53196596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13), 53296596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15), 53396596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_AES_TOP0, "infra_aes_top0", "axi_sel", 16), 53496596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_AES_TOP1, "infra_aes_top1", "axi_sel", 17), 53596596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_SSUSB_BUS, "infra_ssusb_bus", "axi_sel", 18), 53696596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 19), 53796596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 20), 53896596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 21), 53996596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 22), 54096596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_IRTX, "infra_irtx", "spi_sel", 23), 54196596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_SSUSB_SYS, "infra_ssusb_sys", 54296596aa0SKevin-CW Chen "ssusb_top_sys_sel", 24), 54396596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_SSUSB_REF, "infra_ssusb_ref", "clk26m", 9), 54496596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_AUDIO_26M, "infra_audio_26m", "clk26m", 26), 54596596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_AUDIO_26M_PAD_TOP, "infra_audio_26m_pad_top", 54696596aa0SKevin-CW Chen "clk26m", 27), 54796596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share", 54896596aa0SKevin-CW Chen "axi_sel", 28), 54996596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_VAD_WRAP_SOC, "infra_vad_wrap_soc", "axi_sel", 29), 55096596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_DRAMC_CONF, "infra_dramc_conf", "axi_sel", 30), 55196596aa0SKevin-CW Chen GATE_ICG2(CLK_INFRA_DRAMC_B_CONF, "infra_dramc_b_conf", "axi_sel", 31), 55296596aa0SKevin-CW Chen GATE_ICG1(CLK_INFRA_MFG_VCG, "infra_mfg_vcg", "mfg_52m_sel", 14), 55396596aa0SKevin-CW Chen }; 55496596aa0SKevin-CW Chen 55596596aa0SKevin-CW Chen static const struct mtk_fixed_factor infra_fixed_divs[] = { 55696596aa0SKevin-CW Chen FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2), 55796596aa0SKevin-CW Chen }; 55896596aa0SKevin-CW Chen 55996596aa0SKevin-CW Chen static struct clk_onecell_data *infra_clk_data; 56096596aa0SKevin-CW Chen 56196596aa0SKevin-CW Chen static void mtk_infrasys_init_early(struct device_node *node) 56296596aa0SKevin-CW Chen { 56396596aa0SKevin-CW Chen int r, i; 56496596aa0SKevin-CW Chen 56596596aa0SKevin-CW Chen if (!infra_clk_data) { 56696596aa0SKevin-CW Chen infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); 56796596aa0SKevin-CW Chen 56896596aa0SKevin-CW Chen for (i = 0; i < CLK_INFRA_NR; i++) 56996596aa0SKevin-CW Chen infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); 57096596aa0SKevin-CW Chen } 57196596aa0SKevin-CW Chen 57296596aa0SKevin-CW Chen mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), 57396596aa0SKevin-CW Chen infra_clk_data); 57496596aa0SKevin-CW Chen 57596596aa0SKevin-CW Chen r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); 57696596aa0SKevin-CW Chen if (r) 57796596aa0SKevin-CW Chen pr_err("%s(): could not register clock provider: %d\n", 57896596aa0SKevin-CW Chen __func__, r); 57996596aa0SKevin-CW Chen } 58096596aa0SKevin-CW Chen 58196596aa0SKevin-CW Chen CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg", 58296596aa0SKevin-CW Chen mtk_infrasys_init_early); 58396596aa0SKevin-CW Chen 58496596aa0SKevin-CW Chen static int mtk_infrasys_init(struct platform_device *pdev) 58596596aa0SKevin-CW Chen { 58696596aa0SKevin-CW Chen int r, i; 58796596aa0SKevin-CW Chen struct device_node *node = pdev->dev.of_node; 58896596aa0SKevin-CW Chen 58996596aa0SKevin-CW Chen if (!infra_clk_data) { 59096596aa0SKevin-CW Chen infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); 59196596aa0SKevin-CW Chen } else { 59296596aa0SKevin-CW Chen for (i = 0; i < CLK_INFRA_NR; i++) { 59396596aa0SKevin-CW Chen if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) 59496596aa0SKevin-CW Chen infra_clk_data->clks[i] = ERR_PTR(-ENOENT); 59596596aa0SKevin-CW Chen } 59696596aa0SKevin-CW Chen } 59796596aa0SKevin-CW Chen 59896596aa0SKevin-CW Chen mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 59996596aa0SKevin-CW Chen infra_clk_data); 60096596aa0SKevin-CW Chen mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), 60196596aa0SKevin-CW Chen infra_clk_data); 60296596aa0SKevin-CW Chen 60396596aa0SKevin-CW Chen r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); 60496596aa0SKevin-CW Chen if (r) 60596596aa0SKevin-CW Chen return r; 60696596aa0SKevin-CW Chen 60796596aa0SKevin-CW Chen return 0; 60896596aa0SKevin-CW Chen } 60996596aa0SKevin-CW Chen 61096596aa0SKevin-CW Chen #define MT6797_PLL_FMAX (3000UL * MHZ) 61196596aa0SKevin-CW Chen 61296596aa0SKevin-CW Chen #define CON0_MT6797_RST_BAR BIT(24) 61396596aa0SKevin-CW Chen 61496596aa0SKevin-CW Chen #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 61596596aa0SKevin-CW Chen _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 61696596aa0SKevin-CW Chen _pcw_shift, _div_table) { \ 61796596aa0SKevin-CW Chen .id = _id, \ 61896596aa0SKevin-CW Chen .name = _name, \ 61996596aa0SKevin-CW Chen .reg = _reg, \ 62096596aa0SKevin-CW Chen .pwr_reg = _pwr_reg, \ 62196596aa0SKevin-CW Chen .en_mask = _en_mask, \ 62296596aa0SKevin-CW Chen .flags = _flags, \ 62396596aa0SKevin-CW Chen .rst_bar_mask = CON0_MT6797_RST_BAR, \ 62496596aa0SKevin-CW Chen .fmax = MT6797_PLL_FMAX, \ 62596596aa0SKevin-CW Chen .pcwbits = _pcwbits, \ 62696596aa0SKevin-CW Chen .pd_reg = _pd_reg, \ 62796596aa0SKevin-CW Chen .pd_shift = _pd_shift, \ 62896596aa0SKevin-CW Chen .tuner_reg = _tuner_reg, \ 62996596aa0SKevin-CW Chen .pcw_reg = _pcw_reg, \ 63096596aa0SKevin-CW Chen .pcw_shift = _pcw_shift, \ 63196596aa0SKevin-CW Chen .div_table = _div_table, \ 63296596aa0SKevin-CW Chen } 63396596aa0SKevin-CW Chen 63496596aa0SKevin-CW Chen #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 63596596aa0SKevin-CW Chen _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 63696596aa0SKevin-CW Chen _pcw_shift) \ 63796596aa0SKevin-CW Chen PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 63896596aa0SKevin-CW Chen _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ 63996596aa0SKevin-CW Chen NULL) 64096596aa0SKevin-CW Chen 64196596aa0SKevin-CW Chen static const struct mtk_pll_data plls[] = { 64296596aa0SKevin-CW Chen PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000101, PLL_AO, 64396596aa0SKevin-CW Chen 21, 0x220, 4, 0x0, 0x224, 0), 64496596aa0SKevin-CW Chen PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000011, 0, 7, 64596596aa0SKevin-CW Chen 0x230, 4, 0x0, 0x234, 14), 64696596aa0SKevin-CW Chen PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000101, 0, 21, 64796596aa0SKevin-CW Chen 0x244, 24, 0x0, 0x244, 0), 64896596aa0SKevin-CW Chen PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000121, 0, 21, 64996596aa0SKevin-CW Chen 0x250, 4, 0x0, 0x254, 0), 65096596aa0SKevin-CW Chen PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000121, 0, 21, 65196596aa0SKevin-CW Chen 0x260, 4, 0x0, 0x264, 0), 65296596aa0SKevin-CW Chen PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000121, 0, 21, 65396596aa0SKevin-CW Chen 0x270, 4, 0x0, 0x274, 0), 65496596aa0SKevin-CW Chen PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000121, 0, 21, 65596596aa0SKevin-CW Chen 0x290, 4, 0x0, 0x294, 0), 65696596aa0SKevin-CW Chen PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000121, 0, 21, 65796596aa0SKevin-CW Chen 0x2E4, 4, 0x0, 0x2E8, 0), 65896596aa0SKevin-CW Chen PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000131, 0, 31, 65996596aa0SKevin-CW Chen 0x2A0, 4, 0x2A8, 0x2A4, 0), 66096596aa0SKevin-CW Chen PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000131, 0, 31, 66196596aa0SKevin-CW Chen 0x2B4, 4, 0x2BC, 0x2B8, 0), 66296596aa0SKevin-CW Chen }; 66396596aa0SKevin-CW Chen 66496596aa0SKevin-CW Chen static int mtk_apmixedsys_init(struct platform_device *pdev) 66596596aa0SKevin-CW Chen { 66696596aa0SKevin-CW Chen struct clk_onecell_data *clk_data; 66796596aa0SKevin-CW Chen struct device_node *node = pdev->dev.of_node; 66896596aa0SKevin-CW Chen 66996596aa0SKevin-CW Chen clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR); 67096596aa0SKevin-CW Chen if (!clk_data) 67196596aa0SKevin-CW Chen return -ENOMEM; 67296596aa0SKevin-CW Chen 67396596aa0SKevin-CW Chen mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 67496596aa0SKevin-CW Chen 67596596aa0SKevin-CW Chen return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 67696596aa0SKevin-CW Chen } 67796596aa0SKevin-CW Chen 67896596aa0SKevin-CW Chen static const struct of_device_id of_match_clk_mt6797[] = { 67996596aa0SKevin-CW Chen { 68096596aa0SKevin-CW Chen .compatible = "mediatek,mt6797-topckgen", 68196596aa0SKevin-CW Chen .data = mtk_topckgen_init, 68296596aa0SKevin-CW Chen }, { 68396596aa0SKevin-CW Chen .compatible = "mediatek,mt6797-infracfg", 68496596aa0SKevin-CW Chen .data = mtk_infrasys_init, 68596596aa0SKevin-CW Chen }, { 68696596aa0SKevin-CW Chen .compatible = "mediatek,mt6797-apmixedsys", 68796596aa0SKevin-CW Chen .data = mtk_apmixedsys_init, 68896596aa0SKevin-CW Chen }, { 68996596aa0SKevin-CW Chen /* sentinel */ 69096596aa0SKevin-CW Chen } 69196596aa0SKevin-CW Chen }; 69296596aa0SKevin-CW Chen 69396596aa0SKevin-CW Chen static int clk_mt6797_probe(struct platform_device *pdev) 69496596aa0SKevin-CW Chen { 69596596aa0SKevin-CW Chen int (*clk_init)(struct platform_device *); 69696596aa0SKevin-CW Chen int r; 69796596aa0SKevin-CW Chen 69896596aa0SKevin-CW Chen clk_init = of_device_get_match_data(&pdev->dev); 69996596aa0SKevin-CW Chen if (!clk_init) 70096596aa0SKevin-CW Chen return -EINVAL; 70196596aa0SKevin-CW Chen 70296596aa0SKevin-CW Chen r = clk_init(pdev); 70396596aa0SKevin-CW Chen if (r) 70496596aa0SKevin-CW Chen dev_err(&pdev->dev, 70596596aa0SKevin-CW Chen "could not register clock provider: %s: %d\n", 70696596aa0SKevin-CW Chen pdev->name, r); 70796596aa0SKevin-CW Chen 70896596aa0SKevin-CW Chen return r; 70996596aa0SKevin-CW Chen } 71096596aa0SKevin-CW Chen 71196596aa0SKevin-CW Chen static struct platform_driver clk_mt6797_drv = { 71296596aa0SKevin-CW Chen .probe = clk_mt6797_probe, 71396596aa0SKevin-CW Chen .driver = { 71496596aa0SKevin-CW Chen .name = "clk-mt6797", 71596596aa0SKevin-CW Chen .of_match_table = of_match_clk_mt6797, 71696596aa0SKevin-CW Chen }, 71796596aa0SKevin-CW Chen }; 71896596aa0SKevin-CW Chen 71996596aa0SKevin-CW Chen static int __init clk_mt6797_init(void) 72096596aa0SKevin-CW Chen { 72196596aa0SKevin-CW Chen return platform_driver_register(&clk_mt6797_drv); 72296596aa0SKevin-CW Chen } 72396596aa0SKevin-CW Chen 72496596aa0SKevin-CW Chen arch_initcall(clk_mt6797_init); 725