1 /*
2  * Copyright (c) 2017 MediaTek Inc.
3  * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  */
14 
15 #include <linux/clk-provider.h>
16 #include <linux/platform_device.h>
17 #include <dt-bindings/clock/mt6797-clk.h>
18 
19 #include "clk-mtk.h"
20 #include "clk-gate.h"
21 
22 static const struct mtk_gate_regs mm0_cg_regs = {
23 	.set_ofs = 0x0104,
24 	.clr_ofs = 0x0108,
25 	.sta_ofs = 0x0100,
26 };
27 
28 static const struct mtk_gate_regs mm1_cg_regs = {
29 	.set_ofs = 0x0114,
30 	.clr_ofs = 0x0118,
31 	.sta_ofs = 0x0110,
32 };
33 
34 #define GATE_MM0(_id, _name, _parent, _shift) {			\
35 	.id = _id,					\
36 	.name = _name,					\
37 	.parent_name = _parent,				\
38 	.regs = &mm0_cg_regs,				\
39 	.shift = _shift,				\
40 	.ops = &mtk_clk_gate_ops_setclr,		\
41 }
42 
43 #define GATE_MM1(_id, _name, _parent, _shift) {			\
44 	.id = _id,					\
45 	.name = _name,					\
46 	.parent_name = _parent,				\
47 	.regs = &mm1_cg_regs,				\
48 	.shift = _shift,				\
49 	.ops = &mtk_clk_gate_ops_setclr,		\
50 }
51 
52 static const struct mtk_gate mm_clks[] = {
53 	GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
54 	GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
55 	GATE_MM0(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 2),
56 	GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 3),
57 	GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 4),
58 	GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 5),
59 	GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 6),
60 	GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 7),
61 	GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 8),
62 	GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
63 	GATE_MM0(CLK_MM_MDP_COLOR, "mm_mdp_color", "mm_sel", 10),
64 	GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
65 	GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
66 	GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
67 	GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
68 	GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 15),
69 	GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 16),
70 	GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 17),
71 	GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 18),
72 	GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 19),
73 	GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 20),
74 	GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
75 	GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
76 	GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 23),
77 	GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "mm_sel", 24),
78 	GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
79 	GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
80 	GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 27),
81 	GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "mm_sel", 28),
82 	GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 29),
83 	GATE_MM0(CLK_MM_DISP_DSC, "mm_disp_dsc", "mm_sel", 30),
84 	GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
85 	GATE_MM1(CLK_MM_DSI0_MM_CLOCK, "mm_dsi0_mm_clock", "mm_sel", 0),
86 	GATE_MM1(CLK_MM_DSI1_MM_CLOCK, "mm_dsi1_mm_clock", "mm_sel", 2),
87 	GATE_MM1(CLK_MM_DPI_MM_CLOCK, "mm_dpi_mm_clock", "mm_sel", 4),
88 	GATE_MM1(CLK_MM_DPI_INTERFACE_CLOCK, "mm_dpi_interface_clock",
89 		 "dpi0_sel", 5),
90 	GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MM_CLOCK, "mm_larb4_axi_asif_mm_clock",
91 		 "mm_sel", 6),
92 	GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK, "mm_larb4_axi_asif_mjc_clock",
93 		 "mjc_sel", 7),
94 	GATE_MM1(CLK_MM_DISP_OVL0_MOUT_CLOCK, "mm_disp_ovl0_mout_clock",
95 		 "mm_sel", 8),
96 	GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 9),
97 	GATE_MM1(CLK_MM_DSI0_INTERFACE_CLOCK, "mm_dsi0_interface_clock",
98 		 "clk26m", 1),
99 	GATE_MM1(CLK_MM_DSI1_INTERFACE_CLOCK, "mm_dsi1_interface_clock",
100 		 "clk26m", 3),
101 };
102 
103 static const struct of_device_id of_match_clk_mt6797_mm[] = {
104 	{ .compatible = "mediatek,mt6797-mmsys", },
105 	{}
106 };
107 
108 static int clk_mt6797_mm_probe(struct platform_device *pdev)
109 {
110 	struct clk_onecell_data *clk_data;
111 	int r;
112 	struct device_node *node = pdev->dev.of_node;
113 
114 	clk_data = mtk_alloc_clk_data(CLK_MM_NR);
115 
116 	mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
117 			       clk_data);
118 
119 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
120 	if (r)
121 		dev_err(&pdev->dev,
122 			"could not register clock provider: %s: %d\n",
123 			pdev->name, r);
124 
125 	return r;
126 }
127 
128 static struct platform_driver clk_mt6797_mm_drv = {
129 	.probe = clk_mt6797_mm_probe,
130 	.driver = {
131 		.name = "clk-mt6797-mm",
132 		.of_match_table = of_match_clk_mt6797_mm,
133 	},
134 };
135 
136 builtin_platform_driver(clk_mt6797_mm_drv);
137