196596aa0SKevin-CW Chen /* 296596aa0SKevin-CW Chen * Copyright (c) 2017 MediaTek Inc. 396596aa0SKevin-CW Chen * Author: Kevin Chen <kevin-cw.chen@mediatek.com> 496596aa0SKevin-CW Chen * 596596aa0SKevin-CW Chen * This program is free software; you can redistribute it and/or modify 696596aa0SKevin-CW Chen * it under the terms of the GNU General Public License version 2 as 796596aa0SKevin-CW Chen * published by the Free Software Foundation. 896596aa0SKevin-CW Chen * 996596aa0SKevin-CW Chen * This program is distributed in the hope that it will be useful, 1096596aa0SKevin-CW Chen * but WITHOUT ANY WARRANTY; without even the implied warranty of 1196596aa0SKevin-CW Chen * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1296596aa0SKevin-CW Chen * GNU General Public License for more details. 1396596aa0SKevin-CW Chen */ 1496596aa0SKevin-CW Chen 1596596aa0SKevin-CW Chen #include <linux/clk-provider.h> 1696596aa0SKevin-CW Chen #include <linux/platform_device.h> 1796596aa0SKevin-CW Chen #include <dt-bindings/clock/mt6797-clk.h> 1896596aa0SKevin-CW Chen 1996596aa0SKevin-CW Chen #include "clk-mtk.h" 2096596aa0SKevin-CW Chen #include "clk-gate.h" 2196596aa0SKevin-CW Chen 2296596aa0SKevin-CW Chen static const struct mtk_gate_regs mm0_cg_regs = { 2396596aa0SKevin-CW Chen .set_ofs = 0x0104, 2496596aa0SKevin-CW Chen .clr_ofs = 0x0108, 2596596aa0SKevin-CW Chen .sta_ofs = 0x0100, 2696596aa0SKevin-CW Chen }; 2796596aa0SKevin-CW Chen 2896596aa0SKevin-CW Chen static const struct mtk_gate_regs mm1_cg_regs = { 2996596aa0SKevin-CW Chen .set_ofs = 0x0114, 3096596aa0SKevin-CW Chen .clr_ofs = 0x0118, 3196596aa0SKevin-CW Chen .sta_ofs = 0x0110, 3296596aa0SKevin-CW Chen }; 3396596aa0SKevin-CW Chen 3496596aa0SKevin-CW Chen #define GATE_MM0(_id, _name, _parent, _shift) { \ 3596596aa0SKevin-CW Chen .id = _id, \ 3696596aa0SKevin-CW Chen .name = _name, \ 3796596aa0SKevin-CW Chen .parent_name = _parent, \ 3896596aa0SKevin-CW Chen .regs = &mm0_cg_regs, \ 3996596aa0SKevin-CW Chen .shift = _shift, \ 4096596aa0SKevin-CW Chen .ops = &mtk_clk_gate_ops_setclr, \ 4196596aa0SKevin-CW Chen } 4296596aa0SKevin-CW Chen 4396596aa0SKevin-CW Chen #define GATE_MM1(_id, _name, _parent, _shift) { \ 4496596aa0SKevin-CW Chen .id = _id, \ 4596596aa0SKevin-CW Chen .name = _name, \ 4696596aa0SKevin-CW Chen .parent_name = _parent, \ 4796596aa0SKevin-CW Chen .regs = &mm1_cg_regs, \ 4896596aa0SKevin-CW Chen .shift = _shift, \ 4996596aa0SKevin-CW Chen .ops = &mtk_clk_gate_ops_setclr, \ 5096596aa0SKevin-CW Chen } 5196596aa0SKevin-CW Chen 5296596aa0SKevin-CW Chen static const struct mtk_gate mm_clks[] = { 5396596aa0SKevin-CW Chen GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), 5496596aa0SKevin-CW Chen GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), 5596596aa0SKevin-CW Chen GATE_MM0(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 2), 5696596aa0SKevin-CW Chen GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 3), 5796596aa0SKevin-CW Chen GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 4), 5896596aa0SKevin-CW Chen GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 5), 5996596aa0SKevin-CW Chen GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 6), 6096596aa0SKevin-CW Chen GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 7), 6196596aa0SKevin-CW Chen GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 8), 6296596aa0SKevin-CW Chen GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9), 6396596aa0SKevin-CW Chen GATE_MM0(CLK_MM_MDP_COLOR, "mm_mdp_color", "mm_sel", 10), 6496596aa0SKevin-CW Chen GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11), 6596596aa0SKevin-CW Chen GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12), 6696596aa0SKevin-CW Chen GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13), 6796596aa0SKevin-CW Chen GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14), 6896596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 15), 6996596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 16), 7096596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 17), 7196596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 18), 7296596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 19), 7396596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 20), 7496596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21), 7596596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22), 7696596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 23), 7796596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "mm_sel", 24), 7896596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25), 7996596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26), 8096596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 27), 8196596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "mm_sel", 28), 8296596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 29), 8396596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_DSC, "mm_disp_dsc", "mm_sel", 30), 8496596aa0SKevin-CW Chen GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31), 8596596aa0SKevin-CW Chen GATE_MM1(CLK_MM_DSI0_MM_CLOCK, "mm_dsi0_mm_clock", "mm_sel", 0), 8696596aa0SKevin-CW Chen GATE_MM1(CLK_MM_DSI1_MM_CLOCK, "mm_dsi1_mm_clock", "mm_sel", 2), 8796596aa0SKevin-CW Chen GATE_MM1(CLK_MM_DPI_MM_CLOCK, "mm_dpi_mm_clock", "mm_sel", 4), 8896596aa0SKevin-CW Chen GATE_MM1(CLK_MM_DPI_INTERFACE_CLOCK, "mm_dpi_interface_clock", 8996596aa0SKevin-CW Chen "dpi0_sel", 5), 9096596aa0SKevin-CW Chen GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MM_CLOCK, "mm_larb4_axi_asif_mm_clock", 9196596aa0SKevin-CW Chen "mm_sel", 6), 9296596aa0SKevin-CW Chen GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK, "mm_larb4_axi_asif_mjc_clock", 9396596aa0SKevin-CW Chen "mjc_sel", 7), 9496596aa0SKevin-CW Chen GATE_MM1(CLK_MM_DISP_OVL0_MOUT_CLOCK, "mm_disp_ovl0_mout_clock", 9596596aa0SKevin-CW Chen "mm_sel", 8), 9696596aa0SKevin-CW Chen GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 9), 9796596aa0SKevin-CW Chen GATE_MM1(CLK_MM_DSI0_INTERFACE_CLOCK, "mm_dsi0_interface_clock", 9896596aa0SKevin-CW Chen "clk26m", 1), 9996596aa0SKevin-CW Chen GATE_MM1(CLK_MM_DSI1_INTERFACE_CLOCK, "mm_dsi1_interface_clock", 10096596aa0SKevin-CW Chen "clk26m", 3), 10196596aa0SKevin-CW Chen }; 10296596aa0SKevin-CW Chen 10396596aa0SKevin-CW Chen static const struct of_device_id of_match_clk_mt6797_mm[] = { 10496596aa0SKevin-CW Chen { .compatible = "mediatek,mt6797-mmsys", }, 10596596aa0SKevin-CW Chen {} 10696596aa0SKevin-CW Chen }; 10796596aa0SKevin-CW Chen 10896596aa0SKevin-CW Chen static int clk_mt6797_mm_probe(struct platform_device *pdev) 10996596aa0SKevin-CW Chen { 11096596aa0SKevin-CW Chen struct clk_onecell_data *clk_data; 11196596aa0SKevin-CW Chen int r; 11296596aa0SKevin-CW Chen struct device_node *node = pdev->dev.of_node; 11396596aa0SKevin-CW Chen 11496596aa0SKevin-CW Chen clk_data = mtk_alloc_clk_data(CLK_MM_NR); 11596596aa0SKevin-CW Chen 11696596aa0SKevin-CW Chen mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), 11796596aa0SKevin-CW Chen clk_data); 11896596aa0SKevin-CW Chen 11996596aa0SKevin-CW Chen r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 12096596aa0SKevin-CW Chen if (r) 12196596aa0SKevin-CW Chen dev_err(&pdev->dev, 12296596aa0SKevin-CW Chen "could not register clock provider: %s: %d\n", 12396596aa0SKevin-CW Chen pdev->name, r); 12496596aa0SKevin-CW Chen 12596596aa0SKevin-CW Chen return r; 12696596aa0SKevin-CW Chen } 12796596aa0SKevin-CW Chen 12896596aa0SKevin-CW Chen static struct platform_driver clk_mt6797_mm_drv = { 12996596aa0SKevin-CW Chen .probe = clk_mt6797_mm_probe, 13096596aa0SKevin-CW Chen .driver = { 13196596aa0SKevin-CW Chen .name = "clk-mt6797-mm", 13296596aa0SKevin-CW Chen .of_match_table = of_match_clk_mt6797_mm, 13396596aa0SKevin-CW Chen }, 13496596aa0SKevin-CW Chen }; 13596596aa0SKevin-CW Chen 13696596aa0SKevin-CW Chen builtin_platform_driver(clk_mt6797_mm_drv); 137