1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2019 MediaTek Inc.
4  * Author: Wendell Lin <wendell.lin@mediatek.com>
5  */
6 
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 
11 #include "clk-gate.h"
12 #include "clk-mtk.h"
13 #include "clk-mux.h"
14 #include "clk-pll.h"
15 
16 #include <dt-bindings/clock/mt6779-clk.h>
17 
18 static DEFINE_SPINLOCK(mt6779_clk_lock);
19 
20 static const struct mtk_fixed_clk top_fixed_clks[] = {
21 	FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
22 };
23 
24 static const struct mtk_fixed_factor top_divs[] = {
25 	FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
26 	FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2),
27 	FACTOR(CLK_TOP_MAINPLL_CK, "mainpll_ck", "mainpll", 1, 1),
28 	FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll_ck", 1, 2),
29 	FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2),
30 	FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4),
31 	FACTOR(CLK_TOP_MAINPLL_D2_D8, "mainpll_d2_d8", "mainpll_d2", 1, 8),
32 	FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16),
33 	FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
34 	FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2),
35 	FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4),
36 	FACTOR(CLK_TOP_MAINPLL_D3_D8, "mainpll_d3_d8", "mainpll_d3", 1, 8),
37 	FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
38 	FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
39 	FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
40 	FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
41 	FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
42 	FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
43 	FACTOR(CLK_TOP_UNIVPLL_CK, "univpll", "univ2pll", 1, 2),
44 	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
45 	FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2),
46 	FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4),
47 	FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8),
48 	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
49 	FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2),
50 	FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4),
51 	FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8),
52 	FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16),
53 	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
54 	FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
55 	FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
56 	FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
57 	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
58 	FACTOR(CLK_TOP_UNIVP_192M_CK, "univpll_192m_ck", "univ2pll", 1, 13),
59 	FACTOR(CLK_TOP_UNIVP_192M_D2, "univpll_192m_d2", "univpll_192m_ck",
60 	       1, 2),
61 	FACTOR(CLK_TOP_UNIVP_192M_D4, "univpll_192m_d4", "univpll_192m_ck",
62 	       1, 4),
63 	FACTOR(CLK_TOP_UNIVP_192M_D8, "univpll_192m_d8", "univpll_192m_ck",
64 	       1, 8),
65 	FACTOR(CLK_TOP_UNIVP_192M_D16, "univpll_192m_d16", "univpll_192m_ck",
66 	       1, 16),
67 	FACTOR(CLK_TOP_UNIVP_192M_D32, "univpll_192m_d32", "univpll_192m_ck",
68 	       1, 32),
69 	FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
70 	FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
71 	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
72 	FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
73 	FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
74 	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
75 	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
76 	FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
77 	FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
78 	FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
79 	FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
80 	FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
81 	FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
82 	FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1),
83 	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
84 	FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
85 	FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
86 	FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
87 	FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
88 	FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
89 	FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
90 	FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
91 	FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
92 	FACTOR(CLK_TOP_ADSPPLL_CK, "adsppll_ck", "adsppll", 1, 1),
93 	FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
94 	FACTOR(CLK_TOP_ADSPPLL_D5, "adsppll_d5", "adsppll", 1, 5),
95 	FACTOR(CLK_TOP_ADSPPLL_D6, "adsppll_d6", "adsppll", 1, 6),
96 	FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
97 	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
98 	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
99 	FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
100 	FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
101 	FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1),
102 	FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2),
103 	FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4),
104 	FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8),
105 	FACTOR(CLK_TOP_OSC_D10, "osc_d10", "osc", 1, 10),
106 	FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16),
107 	FACTOR(CLK_TOP_AD_OSC2_CK, "ad_osc2_ck", "osc2", 1, 1),
108 	FACTOR(CLK_TOP_OSC2_D2, "osc2_d2", "osc2", 1, 2),
109 	FACTOR(CLK_TOP_OSC2_D3, "osc2_d3", "osc2", 1, 3),
110 	FACTOR(CLK_TOP_TVDPLL_MAINPLL_D2_CK, "tvdpll_mainpll_d2_ck",
111 	       "tvdpll", 1, 1),
112 	FACTOR(CLK_TOP_FMEM_466M_CK, "fmem_466m_ck", "fmem", 1, 1),
113 };
114 
115 static const char * const axi_parents[] = {
116 	"clk26m",
117 	"mainpll_d2_d4",
118 	"mainpll_d7",
119 	"osc_d4"
120 };
121 
122 static const char * const mm_parents[] = {
123 	"clk26m",
124 	"tvdpll_mainpll_d2_ck",
125 	"mmpll_d7",
126 	"mmpll_d5_d2",
127 	"mainpll_d2_d2",
128 	"mainpll_d3_d2"
129 };
130 
131 static const char * const scp_parents[] = {
132 	"clk26m",
133 	"univpll_d2_d8",
134 	"mainpll_d2_d4",
135 	"mainpll_d3",
136 	"univpll_d3",
137 	"ad_osc2_ck",
138 	"osc2_d2",
139 	"osc2_d3"
140 };
141 
142 static const char * const img_parents[] = {
143 	"clk26m",
144 	"mainpll_d2",
145 	"mainpll_d2",
146 	"univpll_d3",
147 	"mainpll_d3",
148 	"mmpll_d5_d2",
149 	"tvdpll_mainpll_d2_ck",
150 	"mainpll_d5"
151 };
152 
153 static const char * const ipe_parents[] = {
154 	"clk26m",
155 	"mainpll_d2",
156 	"mmpll_d7",
157 	"univpll_d3",
158 	"mainpll_d3",
159 	"mmpll_d5_d2",
160 	"mainpll_d2_d2",
161 	"mainpll_d5"
162 };
163 
164 static const char * const dpe_parents[] = {
165 	"clk26m",
166 	"mainpll_d2",
167 	"mmpll_d7",
168 	"univpll_d3",
169 	"mainpll_d3",
170 	"mmpll_d5_d2",
171 	"mainpll_d2_d2",
172 	"mainpll_d5"
173 };
174 
175 static const char * const cam_parents[] = {
176 	"clk26m",
177 	"mainpll_d2",
178 	"mmpll_d6",
179 	"mainpll_d3",
180 	"mmpll_d7",
181 	"univpll_d3",
182 	"mmpll_d5_d2",
183 	"adsppll_d5",
184 	"tvdpll_mainpll_d2_ck",
185 	"univpll_d3_d2"
186 };
187 
188 static const char * const ccu_parents[] = {
189 	"clk26m",
190 	"mainpll_d2",
191 	"mmpll_d6",
192 	"mainpll_d3",
193 	"mmpll_d7",
194 	"univpll_d3",
195 	"mmpll_d5_d2",
196 	"mainpll_d2_d2",
197 	"adsppll_d5",
198 	"univpll_d3_d2"
199 };
200 
201 static const char * const dsp_parents[] = {
202 	"clk26m",
203 	"univpll_d3_d8",
204 	"univpll_d3_d4",
205 	"mainpll_d2_d4",
206 	"univpll_d3_d2",
207 	"mainpll_d2_d2",
208 	"univpll_d2_d2",
209 	"mainpll_d3",
210 	"univpll_d3",
211 	"mmpll_d7",
212 	"mmpll_d6",
213 	"adsppll_d5",
214 	"tvdpll_ck",
215 	"tvdpll_mainpll_d2_ck",
216 	"univpll_d2",
217 	"adsppll_d4"
218 };
219 
220 static const char * const dsp1_parents[] = {
221 	"clk26m",
222 	"univpll_d3_d8",
223 	"univpll_d3_d4",
224 	"mainpll_d2_d4",
225 	"univpll_d3_d2",
226 	"mainpll_d2_d2",
227 	"univpll_d2_d2",
228 	"mainpll_d3",
229 	"univpll_d3",
230 	"mmpll_d7",
231 	"mmpll_d6",
232 	"adsppll_d5",
233 	"tvdpll_ck",
234 	"tvdpll_mainpll_d2_ck",
235 	"univpll_d2",
236 	"adsppll_d4"
237 };
238 
239 static const char * const dsp2_parents[] = {
240 	"clk26m",
241 	"univpll_d3_d8",
242 	"univpll_d3_d4",
243 	"mainpll_d2_d4",
244 	"univpll_d3_d2",
245 	"mainpll_d2_d2",
246 	"univpll_d2_d2",
247 	"mainpll_d3",
248 	"univpll_d3",
249 	"mmpll_d7",
250 	"mmpll_d6",
251 	"adsppll_d5",
252 	"tvdpll_ck",
253 	"tvdpll_mainpll_d2_ck",
254 	"univpll_d2",
255 	"adsppll_d4"
256 };
257 
258 static const char * const dsp3_parents[] = {
259 	"clk26m",
260 	"univpll_d3_d8",
261 	"mainpll_d2_d4",
262 	"univpll_d3_d2",
263 	"mainpll_d2_d2",
264 	"univpll_d2_d2",
265 	"mainpll_d3",
266 	"univpll_d3",
267 	"mmpll_d7",
268 	"mmpll_d6",
269 	"mainpll_d2",
270 	"tvdpll_ck",
271 	"tvdpll_mainpll_d2_ck",
272 	"univpll_d2",
273 	"adsppll_d4",
274 	"mmpll_d4"
275 };
276 
277 static const char * const ipu_if_parents[] = {
278 	"clk26m",
279 	"univpll_d3_d8",
280 	"univpll_d3_d4",
281 	"mainpll_d2_d4",
282 	"univpll_d3_d2",
283 	"mainpll_d2_d2",
284 	"univpll_d2_d2",
285 	"mainpll_d3",
286 	"univpll_d3",
287 	"mmpll_d7",
288 	"mmpll_d6",
289 	"adsppll_d5",
290 	"tvdpll_ck",
291 	"tvdpll_mainpll_d2_ck",
292 	"univpll_d2",
293 	"adsppll_d4"
294 };
295 
296 static const char * const mfg_parents[] = {
297 	"clk26m",
298 	"mfgpll_ck",
299 	"univpll_d3",
300 	"mainpll_d5"
301 };
302 
303 static const char * const f52m_mfg_parents[] = {
304 	"clk26m",
305 	"univpll_d3_d2",
306 	"univpll_d3_d4",
307 	"univpll_d3_d8"
308 };
309 
310 static const char * const camtg_parents[] = {
311 	"clk26m",
312 	"univpll_192m_d8",
313 	"univpll_d3_d8",
314 	"univpll_192m_d4",
315 	"univpll_d3_d16",
316 	"csw_f26m_ck_d2",
317 	"univpll_192m_d16",
318 	"univpll_192m_d32"
319 };
320 
321 static const char * const camtg2_parents[] = {
322 	"clk26m",
323 	"univpll_192m_d8",
324 	"univpll_d3_d8",
325 	"univpll_192m_d4",
326 	"univpll_d3_d16",
327 	"csw_f26m_ck_d2",
328 	"univpll_192m_d16",
329 	"univpll_192m_d32"
330 };
331 
332 static const char * const camtg3_parents[] = {
333 	"clk26m",
334 	"univpll_192m_d8",
335 	"univpll_d3_d8",
336 	"univpll_192m_d4",
337 	"univpll_d3_d16",
338 	"csw_f26m_ck_d2",
339 	"univpll_192m_d16",
340 	"univpll_192m_d32"
341 };
342 
343 static const char * const camtg4_parents[] = {
344 	"clk26m",
345 	"univpll_192m_d8",
346 	"univpll_d3_d8",
347 	"univpll_192m_d4",
348 	"univpll_d3_d16",
349 	"csw_f26m_ck_d2",
350 	"univpll_192m_d16",
351 	"univpll_192m_d32"
352 };
353 
354 static const char * const uart_parents[] = {
355 	"clk26m",
356 	"univpll_d3_d8"
357 };
358 
359 static const char * const spi_parents[] = {
360 	"clk26m",
361 	"mainpll_d5_d2",
362 	"mainpll_d3_d4",
363 	"msdcpll_d4"
364 };
365 
366 static const char * const msdc50_hclk_parents[] = {
367 	"clk26m",
368 	"mainpll_d2_d2",
369 	"mainpll_d3_d2"
370 };
371 
372 static const char * const msdc50_0_parents[] = {
373 	"clk26m",
374 	"msdcpll_ck",
375 	"msdcpll_d2",
376 	"univpll_d2_d4",
377 	"mainpll_d3_d2",
378 	"univpll_d2_d2"
379 };
380 
381 static const char * const msdc30_1_parents[] = {
382 	"clk26m",
383 	"univpll_d3_d2",
384 	"mainpll_d3_d2",
385 	"mainpll_d7",
386 	"msdcpll_d2"
387 };
388 
389 static const char * const audio_parents[] = {
390 	"clk26m",
391 	"mainpll_d5_d4",
392 	"mainpll_d7_d4",
393 	"mainpll_d2_d16"
394 };
395 
396 static const char * const aud_intbus_parents[] = {
397 	"clk26m",
398 	"mainpll_d2_d4",
399 	"mainpll_d7_d2"
400 };
401 
402 static const char * const fpwrap_ulposc_parents[] = {
403 	"osc_d10",
404 	"clk26m",
405 	"osc_d4",
406 	"osc_d8",
407 	"osc_d16"
408 };
409 
410 static const char * const atb_parents[] = {
411 	"clk26m",
412 	"mainpll_d2_d2",
413 	"mainpll_d5"
414 };
415 
416 static const char * const sspm_parents[] = {
417 	"clk26m",
418 	"univpll_d2_d4",
419 	"mainpll_d2_d2",
420 	"univpll_d2_d2",
421 	"mainpll_d3"
422 };
423 
424 static const char * const dpi0_parents[] = {
425 	"clk26m",
426 	"tvdpll_d2",
427 	"tvdpll_d4",
428 	"tvdpll_d8",
429 	"tvdpll_d16"
430 };
431 
432 static const char * const scam_parents[] = {
433 	"clk26m",
434 	"mainpll_d5_d2"
435 };
436 
437 static const char * const disppwm_parents[] = {
438 	"clk26m",
439 	"univpll_d3_d4",
440 	"osc_d2",
441 	"osc_d4",
442 	"osc_d16"
443 };
444 
445 static const char * const usb_top_parents[] = {
446 	"clk26m",
447 	"univpll_d5_d4",
448 	"univpll_d3_d4",
449 	"univpll_d5_d2"
450 };
451 
452 static const char * const ssusb_top_xhci_parents[] = {
453 	"clk26m",
454 	"univpll_d5_d4",
455 	"univpll_d3_d4",
456 	"univpll_d5_d2"
457 };
458 
459 static const char * const spm_parents[] = {
460 	"clk26m",
461 	"osc_d8",
462 	"mainpll_d2_d8"
463 };
464 
465 static const char * const i2c_parents[] = {
466 	"clk26m",
467 	"mainpll_d2_d8",
468 	"univpll_d5_d2"
469 };
470 
471 static const char * const seninf_parents[] = {
472 	"clk26m",
473 	"univpll_d7",
474 	"univpll_d3_d2",
475 	"univpll_d2_d2",
476 	"mainpll_d3",
477 	"mmpll_d4_d2",
478 	"mmpll_d7",
479 	"mmpll_d6"
480 };
481 
482 static const char * const seninf1_parents[] = {
483 	"clk26m",
484 	"univpll_d7",
485 	"univpll_d3_d2",
486 	"univpll_d2_d2",
487 	"mainpll_d3",
488 	"mmpll_d4_d2",
489 	"mmpll_d7",
490 	"mmpll_d6"
491 };
492 
493 static const char * const seninf2_parents[] = {
494 	"clk26m",
495 	"univpll_d7",
496 	"univpll_d3_d2",
497 	"univpll_d2_d2",
498 	"mainpll_d3",
499 	"mmpll_d4_d2",
500 	"mmpll_d7",
501 	"mmpll_d6"
502 };
503 
504 static const char * const dxcc_parents[] = {
505 	"clk26m",
506 	"mainpll_d2_d2",
507 	"mainpll_d2_d4",
508 	"mainpll_d2_d8"
509 };
510 
511 static const char * const aud_engen1_parents[] = {
512 	"clk26m",
513 	"apll1_d2",
514 	"apll1_d4",
515 	"apll1_d8"
516 };
517 
518 static const char * const aud_engen2_parents[] = {
519 	"clk26m",
520 	"apll2_d2",
521 	"apll2_d4",
522 	"apll2_d8"
523 };
524 
525 static const char * const faes_ufsfde_parents[] = {
526 	"clk26m",
527 	"mainpll_d2",
528 	"mainpll_d2_d2",
529 	"mainpll_d3",
530 	"mainpll_d2_d4",
531 	"univpll_d3"
532 };
533 
534 static const char * const fufs_parents[] = {
535 	"clk26m",
536 	"mainpll_d2_d4",
537 	"mainpll_d2_d8",
538 	"mainpll_d2_d16"
539 };
540 
541 static const char * const aud_1_parents[] = {
542 	"clk26m",
543 	"apll1_ck"
544 };
545 
546 static const char * const aud_2_parents[] = {
547 	"clk26m",
548 	"apll2_ck"
549 };
550 
551 static const char * const adsp_parents[] = {
552 	"clk26m",
553 	"mainpll_d3",
554 	"univpll_d2_d4",
555 	"univpll_d2",
556 	"mmpll_d4",
557 	"adsppll_d4",
558 	"adsppll_d6"
559 };
560 
561 static const char * const dpmaif_parents[] = {
562 	"clk26m",
563 	"univpll_d2_d4",
564 	"mainpll_d3",
565 	"mainpll_d2_d2",
566 	"univpll_d2_d2",
567 	"univpll_d3"
568 };
569 
570 static const char * const venc_parents[] = {
571 	"clk26m",
572 	"mmpll_d7",
573 	"mainpll_d3",
574 	"univpll_d2_d2",
575 	"mainpll_d2_d2",
576 	"univpll_d3",
577 	"mmpll_d6",
578 	"mainpll_d5",
579 	"mainpll_d3_d2",
580 	"mmpll_d4_d2",
581 	"univpll_d2_d4",
582 	"mmpll_d5",
583 	"univpll_192m_d2"
584 
585 };
586 
587 static const char * const vdec_parents[] = {
588 	"clk26m",
589 	"univpll_d2_d4",
590 	"mainpll_d3",
591 	"univpll_d2_d2",
592 	"mainpll_d2_d2",
593 	"univpll_d3",
594 	"univpll_d5",
595 	"univpll_d5_d2",
596 	"mainpll_d2",
597 	"univpll_d2",
598 	"univpll_192m_d2"
599 };
600 
601 static const char * const camtm_parents[] = {
602 	"clk26m",
603 	"univpll_d7",
604 	"univpll_d3_d2",
605 	"univpll_d2_d2"
606 };
607 
608 static const char * const pwm_parents[] = {
609 	"clk26m",
610 	"univpll_d2_d8"
611 };
612 
613 static const char * const audio_h_parents[] = {
614 	"clk26m",
615 	"univpll_d7",
616 	"apll1_ck",
617 	"apll2_ck"
618 };
619 
620 static const char * const camtg5_parents[] = {
621 	"clk26m",
622 	"univpll_192m_d8",
623 	"univpll_d3_d8",
624 	"univpll_192m_d4",
625 	"univpll_d3_d16",
626 	"csw_f26m_ck_d2",
627 	"univpll_192m_d16",
628 	"univpll_192m_d32"
629 };
630 
631 /*
632  * CRITICAL CLOCK:
633  * axi_sel is the main bus clock of whole SOC.
634  * spm_sel is the clock of the always-on co-processor.
635  * sspm_sel is the clock of the always-on co-processor.
636  */
637 static const struct mtk_mux top_muxes[] = {
638 	/* CLK_CFG_0 */
639 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents,
640 				   0x20, 0x24, 0x28, 0, 2, 7,
641 				   0x004, 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
642 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
643 			     0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
644 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
645 			     0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2),
646 	/* CLK_CFG_1 */
647 	MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents,
648 			     0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4),
649 	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents,
650 			     0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5),
651 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents,
652 			     0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6),
653 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents,
654 			     0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7),
655 	/* CLK_CFG_2 */
656 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents,
657 			     0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8),
658 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents,
659 			     0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9),
660 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents,
661 			     0x40, 0x44, 0x48, 16, 4, 23, 0x004, 10),
662 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "dsp2_sel", dsp2_parents,
663 			     0x40, 0x44, 0x48, 24, 4, 31, 0x004, 11),
664 	/* CLK_CFG_3 */
665 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "dsp3_sel", dsp3_parents,
666 			     0x50, 0x54, 0x58, 0, 4, 7, 0x004, 12),
667 	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "ipu_if_sel", ipu_if_parents,
668 			     0x50, 0x54, 0x58, 8, 4, 15, 0x004, 13),
669 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "mfg_sel", mfg_parents,
670 			     0x50, 0x54, 0x58, 16, 2, 23, 0x004, 14),
671 	MUX_GATE_CLR_SET_UPD(CLK_TOP_F52M_MFG, "f52m_mfg_sel",
672 			     f52m_mfg_parents, 0x50, 0x54, 0x58,
673 			     24, 2, 31, 0x004, 15),
674 	/* CLK_CFG_4 */
675 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "camtg_sel", camtg_parents,
676 			     0x60, 0x64, 0x68, 0, 3, 7, 0x004, 16),
677 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "camtg2_sel", camtg2_parents,
678 			     0x60, 0x64, 0x68, 8, 3, 15, 0x004, 17),
679 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "camtg3_sel", camtg3_parents,
680 			     0x60, 0x64, 0x68, 16, 3, 23, 0x004, 18),
681 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "camtg4_sel", camtg4_parents,
682 			     0x60, 0x64, 0x68, 24, 3, 31, 0x004, 19),
683 	/* CLK_CFG_5 */
684 	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
685 			     0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20),
686 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
687 			     0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21),
688 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
689 				   msdc50_hclk_parents, 0x70, 0x74, 0x78,
690 				   16, 2, 23, 0x004, 22, 0),
691 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "msdc50_0_sel",
692 				   msdc50_0_parents, 0x70, 0x74, 0x78,
693 				   24, 3, 31, 0x004, 23, 0),
694 	/* CLK_CFG_6 */
695 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "msdc30_1_sel",
696 				   msdc30_1_parents, 0x80, 0x84, 0x88,
697 				   0, 3, 7, 0x004, 24, 0),
698 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents,
699 			     0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25),
700 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",
701 			     aud_intbus_parents, 0x80, 0x84, 0x88,
702 			     16, 2, 23, 0x004, 26),
703 	MUX_GATE_CLR_SET_UPD(CLK_TOP_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
704 			     fpwrap_ulposc_parents, 0x80, 0x84, 0x88,
705 			     24, 3, 31, 0x004, 27),
706 	/* CLK_CFG_7 */
707 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "atb_sel", atb_parents,
708 			     0x90, 0x94, 0x98, 0, 2, 7, 0x004, 28),
709 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents,
710 				   0x90, 0x94, 0x98, 8, 3, 15,
711 				   0x004, 29, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
712 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents,
713 			     0x90, 0x94, 0x98, 16, 3, 23, 0x004, 30),
714 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents,
715 			     0x90, 0x94, 0x98, 24, 1, 31, 0x004, 0),
716 	/* CLK_CFG_8 */
717 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disppwm_sel",
718 			     disppwm_parents, 0xa0, 0xa4, 0xa8,
719 			     0, 3, 7, 0x008, 1),
720 	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "usb_top_sel",
721 			     usb_top_parents, 0xa0, 0xa4, 0xa8,
722 			     8, 2, 15, 0x008, 2),
723 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
724 			     ssusb_top_xhci_parents, 0xa0, 0xa4, 0xa8,
725 			     16, 2, 23, 0x008, 3),
726 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents,
727 				   0xa0, 0xa4, 0xa8, 24, 2, 31,
728 				   0x008, 4, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
729 	/* CLK_CFG_9 */
730 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents,
731 			     0xb0, 0xb4, 0xb8, 0, 2, 7, 0x008, 5),
732 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "seninf_sel", seninf_parents,
733 			     0xb0, 0xb4, 0xb8, 8, 2, 15, 0x008, 6),
734 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "seninf1_sel",
735 			     seninf1_parents, 0xb0, 0xb4, 0xb8,
736 			     16, 2, 23, 0x008, 7),
737 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "seninf2_sel",
738 			     seninf2_parents, 0xb0, 0xb4, 0xb8,
739 			     24, 2, 31, 0x008, 8),
740 	/* CLK_CFG_10 */
741 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc_sel", dxcc_parents,
742 			     0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 9),
743 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG1, "aud_eng1_sel",
744 			     aud_engen1_parents, 0xc0, 0xc4, 0xc8,
745 			     8, 2, 15, 0x008, 10),
746 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG2, "aud_eng2_sel",
747 			     aud_engen2_parents, 0xc0, 0xc4, 0xc8,
748 			     16, 2, 23, 0x008, 11),
749 	MUX_GATE_CLR_SET_UPD(CLK_TOP_FAES_UFSFDE, "faes_ufsfde_sel",
750 			     faes_ufsfde_parents, 0xc0, 0xc4, 0xc8,
751 			     24, 3, 31,
752 			     0x008, 12),
753 	/* CLK_CFG_11 */
754 	MUX_GATE_CLR_SET_UPD(CLK_TOP_FUFS, "fufs_sel", fufs_parents,
755 			     0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 13),
756 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1_sel", aud_1_parents,
757 			     0xd0, 0xd4, 0xd8, 8, 1, 15, 0x008, 14),
758 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2_sel", aud_2_parents,
759 			     0xd0, 0xd4, 0xd8, 16, 1, 23, 0x008, 15),
760 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "adsp_sel", adsp_parents,
761 			     0xd0, 0xd4, 0xd8, 24, 3, 31, 0x008, 16),
762 	/* CLK_CFG_12 */
763 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "dpmaif_sel", dpmaif_parents,
764 			     0xe0, 0xe4, 0xe8, 0, 3, 7, 0x008, 17),
765 	MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "venc_sel", venc_parents,
766 			     0xe0, 0xe4, 0xe8, 8, 4, 15, 0x008, 18),
767 	MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "vdec_sel", vdec_parents,
768 			     0xe0, 0xe4, 0xe8, 16, 4, 23, 0x008, 19),
769 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "camtm_sel", camtm_parents,
770 			     0xe0, 0xe4, 0xe8, 24, 2, 31, 0x004, 20),
771 	/* CLK_CFG_13 */
772 	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "pwm_sel", pwm_parents,
773 			     0xf0, 0xf4, 0xf8, 0, 1, 7, 0x008, 21),
774 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_H, "audio_h_sel",
775 			     audio_h_parents, 0xf0, 0xf4, 0xf8,
776 			     8, 2, 15, 0x008, 22),
777 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "camtg5_sel", camtg5_parents,
778 			     0xf0, 0xf4, 0xf8, 24, 3, 31, 0x008, 24),
779 };
780 
781 static const char * const i2s0_m_ck_parents[] = {
782 	"aud_1_sel",
783 	"aud_2_sel"
784 };
785 
786 static const char * const i2s1_m_ck_parents[] = {
787 	"aud_1_sel",
788 	"aud_2_sel"
789 };
790 
791 static const char * const i2s2_m_ck_parents[] = {
792 	"aud_1_sel",
793 	"aud_2_sel"
794 };
795 
796 static const char * const i2s3_m_ck_parents[] = {
797 	"aud_1_sel",
798 	"aud_2_sel"
799 };
800 
801 static const char * const i2s4_m_ck_parents[] = {
802 	"aud_1_sel",
803 	"aud_2_sel"
804 };
805 
806 static const char * const i2s5_m_ck_parents[] = {
807 	"aud_1_sel",
808 	"aud_2_sel"
809 };
810 
811 static const struct mtk_composite top_aud_muxes[] = {
812 	MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents,
813 	    0x320, 8, 1),
814 	MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents,
815 	    0x320, 9, 1),
816 	MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents,
817 	    0x320, 10, 1),
818 	MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents,
819 	    0x320, 11, 1),
820 	MUX(CLK_TOP_I2S4_M_SEL, "i2s4_m_ck_sel", i2s4_m_ck_parents,
821 	    0x320, 12, 1),
822 	MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents,
823 	    0x328, 20, 1),
824 };
825 
826 static struct mtk_composite top_aud_divs[] = {
827 	DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
828 		 0x320, 2, 0x324, 8, 0),
829 	DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel",
830 		 0x320, 3, 0x324, 8, 8),
831 	DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2s2_m_ck_sel",
832 		 0x320, 4, 0x324, 8, 16),
833 	DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2s3_m_ck_sel",
834 		 0x320, 5, 0x324, 8, 24),
835 	DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel",
836 		 0x320, 6, 0x328, 8, 0),
837 	DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
838 		 0x320, 7, 0x328, 8, 8),
839 	DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel",
840 		 0x328, 16, 0x328, 4, 28),
841 };
842 
843 static const struct mtk_gate_regs infra0_cg_regs = {
844 	.set_ofs = 0x80,
845 	.clr_ofs = 0x84,
846 	.sta_ofs = 0x90,
847 };
848 
849 static const struct mtk_gate_regs infra1_cg_regs = {
850 	.set_ofs = 0x88,
851 	.clr_ofs = 0x8c,
852 	.sta_ofs = 0x94,
853 };
854 
855 static const struct mtk_gate_regs infra2_cg_regs = {
856 	.set_ofs = 0xa4,
857 	.clr_ofs = 0xa8,
858 	.sta_ofs = 0xac,
859 };
860 
861 static const struct mtk_gate_regs infra3_cg_regs = {
862 	.set_ofs = 0xc0,
863 	.clr_ofs = 0xc4,
864 	.sta_ofs = 0xc8,
865 };
866 
867 #define GATE_INFRA0(_id, _name, _parent, _shift)		\
868 	GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift,	\
869 		&mtk_clk_gate_ops_setclr)
870 #define GATE_INFRA1(_id, _name, _parent, _shift)		\
871 	GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift,	\
872 		&mtk_clk_gate_ops_setclr)
873 #define GATE_INFRA2(_id, _name, _parent, _shift)		\
874 	GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift,	\
875 		&mtk_clk_gate_ops_setclr)
876 #define GATE_INFRA3(_id, _name, _parent, _shift)		\
877 	GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift,	\
878 		&mtk_clk_gate_ops_setclr)
879 
880 static const struct mtk_gate infra_clks[] = {
881 	GATE_DUMMY(CLK_DUMMY, "ifa_dummy"),
882 	/* INFRA0 */
883 	GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
884 		    "axi_sel", 0),
885 	GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
886 		    "axi_sel", 1),
887 	GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
888 		    "axi_sel", 2),
889 	GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
890 		    "axi_sel", 3),
891 	GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
892 		    "axi_sel", 4),
893 	GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
894 		    "f_f26m_ck", 5),
895 	GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
896 		    "axi_sel", 6),
897 	GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
898 		    "axi_sel", 8),
899 	GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
900 		    "axi_sel", 9),
901 	GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
902 		    "axi_sel", 10),
903 	GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
904 		    "i2c_sel", 11),
905 	GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
906 		    "i2c_sel", 12),
907 	GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
908 		    "i2c_sel", 13),
909 	GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
910 		    "i2c_sel", 14),
911 	GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
912 		    "pwm_sel", 15),
913 	GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
914 		    "pwm_sel", 16),
915 	GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
916 		    "pwm_sel", 17),
917 	GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
918 		    "pwm_sel", 18),
919 	GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
920 		    "pwm_sel", 19),
921 	GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
922 		    "pwm_sel", 21),
923 	GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
924 		    "uart_sel", 22),
925 	GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
926 		    "uart_sel", 23),
927 	GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
928 		    "uart_sel", 24),
929 	GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
930 		    "uart_sel", 25),
931 	GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
932 		    "axi_sel", 27),
933 	GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
934 		    "axi_sel", 28),
935 	GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
936 		    "axi_sel", 31),
937 	/* INFRA1 */
938 	GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
939 		    "spi_sel", 1),
940 	GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
941 		    "msdc50_hclk_sel", 2),
942 	GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
943 		    "axi_sel", 4),
944 	GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
945 		    "axi_sel", 5),
946 	GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
947 		    "msdc50_0_sel", 6),
948 	GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
949 		    "f_f26m_ck", 7),
950 	GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
951 		    "axi_sel", 8),
952 	GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
953 		    "axi_sel", 9),
954 	GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
955 		    "f_f26m_ck", 10),
956 	GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
957 		    "axi_sel", 11),
958 	GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
959 		    "axi_sel", 12),
960 	GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
961 		    "axi_sel", 13),
962 	GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
963 		    "f_f26m_ck", 14),
964 	GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
965 		    "msdc30_1_sel", 16),
966 	GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
967 		    "msdc30_2_sel", 17),
968 	GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
969 		    "axi_sel", 18),
970 	GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
971 		    "axi_sel", 19),
972 	GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
973 		    "axi_sel", 20),
974 	GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
975 		    "axi_sel", 23),
976 	GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
977 		    "axi_sel", 24),
978 	GATE_INFRA1(CLK_INFRA_AUD, "infra_audio",
979 		    "axi_sel", 25),
980 	GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
981 		    "axi_sel", 26),
982 	GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
983 		    "dxcc_sel", 27),
984 	GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
985 		    "dxcc_sel", 28),
986 	GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
987 		    "axi_sel", 30),
988 	GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
989 		    "f_f26m_ck", 31),
990 	/* INFRA2 */
991 	GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
992 		    "f_f26m_ck", 0),
993 	GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
994 		    "usb_top_sel", 1),
995 	GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
996 		    "axi_sel", 2),
997 	GATE_INFRA2(CLK_INFRA_AUD_26M_BCLK,
998 		    "infracfg_ao_audio_26m_bclk", "f_f26m_ck", 4),
999 	GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
1000 		    "spi_sel", 6),
1001 	GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
1002 		    "i2c_sel", 7),
1003 	GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
1004 		    "f_f26m_ck", 8),
1005 	GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
1006 		    "spi_sel", 9),
1007 	GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
1008 		    "spi_sel", 10),
1009 	GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
1010 		    "fufs_sel", 11),
1011 	GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
1012 		    "fufs_sel", 12),
1013 	GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
1014 		    "fufs_sel", 13),
1015 	GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
1016 		    "axi_sel", 14),
1017 	GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
1018 		    "axi_sel", 16),
1019 	GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
1020 		    "axi_sel", 17),
1021 	GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
1022 		    "i2c_sel", 18),
1023 	GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
1024 		    "i2c_sel", 19),
1025 	GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
1026 		    "i2c_sel", 20),
1027 	GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
1028 		    "i2c_sel", 21),
1029 	GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
1030 		    "i2c_sel", 22),
1031 	GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
1032 		    "i2c_sel", 23),
1033 	GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
1034 		    "i2c_sel", 24),
1035 	GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
1036 		    "spi_sel", 25),
1037 	GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
1038 		    "spi_sel", 26),
1039 	GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
1040 		    "axi_sel", 27),
1041 	GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
1042 		    "fufs_sel", 28),
1043 	GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
1044 		    "faes_ufsfde_sel", 29),
1045 	GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
1046 		    "fufs_sel", 30),
1047 	GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci",
1048 		    "ssusb_top_xhci_sel", 31),
1049 	/* INFRA3 */
1050 	GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
1051 		    "msdc50_0_sel", 0),
1052 	GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
1053 		    "msdc50_0_sel", 1),
1054 	GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
1055 		    "msdc50_0_sel", 2),
1056 	GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
1057 		    "f_f26m_ck", 3),
1058 	GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
1059 		    "f_f26m_ck", 4),
1060 	GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
1061 		    "axi_sel", 5),
1062 	GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
1063 		    "i2c_sel", 6),
1064 	GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
1065 		    "msdc50_hclk_sel", 7),
1066 	GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
1067 		    "msdc50_hclk_sel", 8),
1068 	GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
1069 		    "axi_sel", 16),
1070 	GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
1071 		    "axi_sel", 17),
1072 	GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
1073 		    "axi_sel", 18),
1074 	GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
1075 		    "axi_sel", 19),
1076 	GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
1077 		    "f_f26m_ck", 20),
1078 	GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
1079 		    "axi_sel", 21),
1080 	GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
1081 		    "i2c_sel", 22),
1082 	GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
1083 		    "i2c_sel", 23),
1084 	GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
1085 		    "msdc50_0_sel", 24),
1086 	GATE_INFRA3(CLK_INFRA_DPMAIF_CK, "infra_dpmaif",
1087 		    "dpmaif_sel", 26),
1088 	GATE_INFRA3(CLK_INFRA_FADSP, "infra_fadsp",
1089 		    "adsp_sel", 27),
1090 	GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap",
1091 		    "axi_sel", 28),
1092 	GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md",
1093 		    "axi_sel", 29),
1094 	GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6",
1095 		    "spi_sel", 30),
1096 	GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7",
1097 		    "spi_sel", 31),
1098 };
1099 
1100 static const struct mtk_gate_regs apmixed_cg_regs = {
1101 	.set_ofs = 0x20,
1102 	.clr_ofs = 0x20,
1103 	.sta_ofs = 0x20,
1104 };
1105 
1106 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags)	\
1107 	GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs,		\
1108 		_shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
1109 
1110 #define GATE_APMIXED(_id, _name, _parent, _shift)	\
1111 	GATE_APMIXED_FLAGS(_id, _name, _parent, _shift,	0)
1112 
1113 /*
1114  * CRITICAL CLOCK:
1115  * apmixed_appll26m is the toppest clock gate of all PLLs.
1116  */
1117 static const struct mtk_gate apmixed_clks[] = {
1118 	GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m",
1119 		     "f_f26m_ck", 4),
1120 	GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL26M, "apmixed_appll26m",
1121 			   "f_f26m_ck", 5, CLK_IS_CRITICAL),
1122 	GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
1123 		     "f_f26m_ck", 6),
1124 	GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m",
1125 		     "f_f26m_ck", 7),
1126 	GATE_APMIXED(CLK_APMIXED_MM_F26M, "apmixed_mmsys26m",
1127 		     "f_f26m_ck", 8),
1128 	GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m",
1129 		     "f_f26m_ck", 9),
1130 	GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
1131 		     "f_f26m_ck", 11),
1132 	GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m",
1133 		     "f_f26m_ck", 13),
1134 	GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
1135 		     "f_f26m_ck", 14),
1136 	GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
1137 		     "f_f26m_ck", 16),
1138 	GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
1139 		     "f_f26m_ck", 17),
1140 };
1141 
1142 #define MT6779_PLL_FMAX		(3800UL * MHZ)
1143 #define MT6779_PLL_FMIN		(1500UL * MHZ)
1144 
1145 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,		\
1146 			_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg,	\
1147 			_pd_shift, _tuner_reg,  _tuner_en_reg,		\
1148 			_tuner_en_bit, _pcw_reg, _pcw_shift,		\
1149 			_pcw_chg_reg, _div_table) {			\
1150 		.id = _id,						\
1151 		.name = _name,						\
1152 		.reg = _reg,						\
1153 		.pwr_reg = _pwr_reg,					\
1154 		.en_mask = _en_mask,					\
1155 		.flags = _flags,					\
1156 		.rst_bar_mask = _rst_bar_mask,				\
1157 		.fmax = MT6779_PLL_FMAX,				\
1158 		.fmin = MT6779_PLL_FMIN,				\
1159 		.pcwbits = _pcwbits,					\
1160 		.pcwibits = _pcwibits,					\
1161 		.pd_reg = _pd_reg,					\
1162 		.pd_shift = _pd_shift,					\
1163 		.tuner_reg = _tuner_reg,				\
1164 		.tuner_en_reg = _tuner_en_reg,				\
1165 		.tuner_en_bit = _tuner_en_bit,				\
1166 		.pcw_reg = _pcw_reg,					\
1167 		.pcw_shift = _pcw_shift,				\
1168 		.pcw_chg_reg = _pcw_chg_reg,				\
1169 		.div_table = _div_table,				\
1170 	}
1171 
1172 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,		\
1173 			_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg,	\
1174 			_pd_shift, _tuner_reg, _tuner_en_reg,		\
1175 			_tuner_en_bit, _pcw_reg, _pcw_shift,		\
1176 			_pcw_chg_reg)					\
1177 		PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,	\
1178 			_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg,	\
1179 			_pd_shift, _tuner_reg, _tuner_en_reg,		\
1180 			_tuner_en_bit, _pcw_reg, _pcw_shift,		\
1181 			_pcw_chg_reg, NULL)
1182 
1183 static const struct mtk_pll_data plls[] = {
1184 	PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
1185 	    PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0),
1186 	PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, 0,
1187 	    PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0),
1188 	PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, 0,
1189 	    PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0),
1190 	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0,
1191 	    (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0,
1192 	    0x0234, 0, 0),
1193 	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, 0,
1194 	    (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24,
1195 	    0, 0, 0, 0x0244, 0, 0),
1196 	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, 0,
1197 	    0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0),
1198 	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, 0,
1199 	    0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0),
1200 	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0,
1201 	    0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0),
1202 	PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, 0,
1203 	    (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24,
1204 	    0, 0, 0, 0x02b4, 0, 0),
1205 	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, 0,
1206 	    (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24,
1207 	    0, 0, 0, 0x0284, 0, 0),
1208 	PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, 0,
1209 	    0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0),
1210 	PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, 0,
1211 	    0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),
1212 };
1213 
1214 static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
1215 {
1216 	struct clk_hw_onecell_data *clk_data;
1217 	struct device_node *node = pdev->dev.of_node;
1218 
1219 	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1220 	if (!clk_data)
1221 		return -ENOMEM;
1222 
1223 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1224 
1225 	mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
1226 			       ARRAY_SIZE(apmixed_clks), clk_data);
1227 
1228 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1229 }
1230 
1231 static int clk_mt6779_top_probe(struct platform_device *pdev)
1232 {
1233 	void __iomem *base;
1234 	struct clk_hw_onecell_data *clk_data;
1235 	struct device_node *node = pdev->dev.of_node;
1236 
1237 	base = devm_platform_ioremap_resource(pdev, 0);
1238 	if (IS_ERR(base))
1239 		return PTR_ERR(base);
1240 
1241 	clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1242 	if (!clk_data)
1243 		return -ENOMEM;
1244 
1245 	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1246 				    clk_data);
1247 
1248 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
1249 
1250 	mtk_clk_register_muxes(&pdev->dev, top_muxes,
1251 			       ARRAY_SIZE(top_muxes), node,
1252 			       &mt6779_clk_lock, clk_data);
1253 
1254 	mtk_clk_register_composites(&pdev->dev, top_aud_muxes,
1255 				    ARRAY_SIZE(top_aud_muxes), base,
1256 				    &mt6779_clk_lock, clk_data);
1257 
1258 	mtk_clk_register_composites(&pdev->dev, top_aud_divs,
1259 				    ARRAY_SIZE(top_aud_divs), base,
1260 				    &mt6779_clk_lock, clk_data);
1261 
1262 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1263 }
1264 
1265 static const struct of_device_id of_match_clk_mt6779[] = {
1266 	{
1267 		.compatible = "mediatek,mt6779-apmixed",
1268 		.data = clk_mt6779_apmixed_probe,
1269 	}, {
1270 		.compatible = "mediatek,mt6779-topckgen",
1271 		.data = clk_mt6779_top_probe,
1272 	}, {
1273 		/* sentinel */
1274 	}
1275 };
1276 
1277 static int clk_mt6779_probe(struct platform_device *pdev)
1278 {
1279 	int (*clk_probe)(struct platform_device *pdev);
1280 	int r;
1281 
1282 	clk_probe = of_device_get_match_data(&pdev->dev);
1283 	if (!clk_probe)
1284 		return -EINVAL;
1285 
1286 	r = clk_probe(pdev);
1287 	if (r)
1288 		dev_err(&pdev->dev,
1289 			"could not register clock provider: %s: %d\n",
1290 			pdev->name, r);
1291 
1292 	return r;
1293 }
1294 
1295 static const struct mtk_clk_desc infra_desc = {
1296 	.clks = infra_clks,
1297 	.num_clks = ARRAY_SIZE(infra_clks),
1298 };
1299 
1300 static const struct of_device_id of_match_clk_mt6779_infra[] = {
1301 	{ .compatible = "mediatek,mt6779-infracfg_ao", .data = &infra_desc },
1302 	{ /* sentinel */ }
1303 };
1304 MODULE_DEVICE_TABLE(of, of_match_clk_mt6779);
1305 
1306 static struct platform_driver clk_mt6779_infra_drv  = {
1307 	.probe = mtk_clk_simple_probe,
1308 	.remove_new = mtk_clk_simple_remove,
1309 	.driver = {
1310 		.name = "clk-mt6779-infra",
1311 		.of_match_table = of_match_clk_mt6779_infra,
1312 	},
1313 };
1314 
1315 static struct platform_driver clk_mt6779_drv = {
1316 	.probe = clk_mt6779_probe,
1317 	.driver = {
1318 		.name = "clk-mt6779",
1319 		.of_match_table = of_match_clk_mt6779,
1320 	},
1321 };
1322 
1323 static int __init clk_mt6779_init(void)
1324 {
1325 	int ret = platform_driver_register(&clk_mt6779_drv);
1326 
1327 	if (ret)
1328 		return ret;
1329 	return platform_driver_register(&clk_mt6779_infra_drv);
1330 }
1331 
1332 arch_initcall(clk_mt6779_init);
1333 MODULE_LICENSE("GPL");
1334