1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Author: Wendell Lin <wendell.lin@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/of_device.h> 11 #include <linux/platform_device.h> 12 13 #include "clk-gate.h" 14 #include "clk-mtk.h" 15 #include "clk-mux.h" 16 #include "clk-pll.h" 17 18 #include <dt-bindings/clock/mt6779-clk.h> 19 20 static DEFINE_SPINLOCK(mt6779_clk_lock); 21 22 static const struct mtk_fixed_clk top_fixed_clks[] = { 23 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000), 24 }; 25 26 static const struct mtk_fixed_factor top_divs[] = { 27 FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2), 28 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2), 29 FACTOR(CLK_TOP_MAINPLL_CK, "mainpll_ck", "mainpll", 1, 1), 30 FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll_ck", 1, 2), 31 FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2), 32 FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4), 33 FACTOR(CLK_TOP_MAINPLL_D2_D8, "mainpll_d2_d8", "mainpll_d2", 1, 8), 34 FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16), 35 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3), 36 FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2), 37 FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4), 38 FACTOR(CLK_TOP_MAINPLL_D3_D8, "mainpll_d3_d8", "mainpll_d3", 1, 8), 39 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5), 40 FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2), 41 FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4), 42 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7), 43 FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2), 44 FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4), 45 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll", "univ2pll", 1, 2), 46 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 47 FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2), 48 FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4), 49 FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8), 50 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 51 FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2), 52 FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4), 53 FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8), 54 FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16), 55 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 56 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2), 57 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4), 58 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8), 59 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 60 FACTOR(CLK_TOP_UNIVP_192M_CK, "univpll_192m_ck", "univ2pll", 1, 13), 61 FACTOR(CLK_TOP_UNIVP_192M_D2, "univpll_192m_d2", "univpll_192m_ck", 62 1, 2), 63 FACTOR(CLK_TOP_UNIVP_192M_D4, "univpll_192m_d4", "univpll_192m_ck", 64 1, 4), 65 FACTOR(CLK_TOP_UNIVP_192M_D8, "univpll_192m_d8", "univpll_192m_ck", 66 1, 8), 67 FACTOR(CLK_TOP_UNIVP_192M_D16, "univpll_192m_d16", "univpll_192m_ck", 68 1, 16), 69 FACTOR(CLK_TOP_UNIVP_192M_D32, "univpll_192m_d32", "univpll_192m_ck", 70 1, 32), 71 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1), 72 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2), 73 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4), 74 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8), 75 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1), 76 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), 77 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), 78 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8), 79 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1), 80 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), 81 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 82 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8), 83 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16), 84 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1), 85 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), 86 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2), 87 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4), 88 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 89 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2), 90 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4), 91 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), 92 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 93 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1), 94 FACTOR(CLK_TOP_ADSPPLL_CK, "adsppll_ck", "adsppll", 1, 1), 95 FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4), 96 FACTOR(CLK_TOP_ADSPPLL_D5, "adsppll_d5", "adsppll", 1, 5), 97 FACTOR(CLK_TOP_ADSPPLL_D6, "adsppll_d6", "adsppll", 1, 6), 98 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1), 99 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 100 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 101 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8), 102 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16), 103 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1), 104 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2), 105 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4), 106 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8), 107 FACTOR(CLK_TOP_OSC_D10, "osc_d10", "osc", 1, 10), 108 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16), 109 FACTOR(CLK_TOP_AD_OSC2_CK, "ad_osc2_ck", "osc2", 1, 1), 110 FACTOR(CLK_TOP_OSC2_D2, "osc2_d2", "osc2", 1, 2), 111 FACTOR(CLK_TOP_OSC2_D3, "osc2_d3", "osc2", 1, 3), 112 FACTOR(CLK_TOP_TVDPLL_MAINPLL_D2_CK, "tvdpll_mainpll_d2_ck", 113 "tvdpll", 1, 1), 114 FACTOR(CLK_TOP_FMEM_466M_CK, "fmem_466m_ck", "fmem", 1, 1), 115 }; 116 117 static const char * const axi_parents[] = { 118 "clk26m", 119 "mainpll_d2_d4", 120 "mainpll_d7", 121 "osc_d4" 122 }; 123 124 static const char * const mm_parents[] = { 125 "clk26m", 126 "tvdpll_mainpll_d2_ck", 127 "mmpll_d7", 128 "mmpll_d5_d2", 129 "mainpll_d2_d2", 130 "mainpll_d3_d2" 131 }; 132 133 static const char * const scp_parents[] = { 134 "clk26m", 135 "univpll_d2_d8", 136 "mainpll_d2_d4", 137 "mainpll_d3", 138 "univpll_d3", 139 "ad_osc2_ck", 140 "osc2_d2", 141 "osc2_d3" 142 }; 143 144 static const char * const img_parents[] = { 145 "clk26m", 146 "mainpll_d2", 147 "mainpll_d2", 148 "univpll_d3", 149 "mainpll_d3", 150 "mmpll_d5_d2", 151 "tvdpll_mainpll_d2_ck", 152 "mainpll_d5" 153 }; 154 155 static const char * const ipe_parents[] = { 156 "clk26m", 157 "mainpll_d2", 158 "mmpll_d7", 159 "univpll_d3", 160 "mainpll_d3", 161 "mmpll_d5_d2", 162 "mainpll_d2_d2", 163 "mainpll_d5" 164 }; 165 166 static const char * const dpe_parents[] = { 167 "clk26m", 168 "mainpll_d2", 169 "mmpll_d7", 170 "univpll_d3", 171 "mainpll_d3", 172 "mmpll_d5_d2", 173 "mainpll_d2_d2", 174 "mainpll_d5" 175 }; 176 177 static const char * const cam_parents[] = { 178 "clk26m", 179 "mainpll_d2", 180 "mmpll_d6", 181 "mainpll_d3", 182 "mmpll_d7", 183 "univpll_d3", 184 "mmpll_d5_d2", 185 "adsppll_d5", 186 "tvdpll_mainpll_d2_ck", 187 "univpll_d3_d2" 188 }; 189 190 static const char * const ccu_parents[] = { 191 "clk26m", 192 "mainpll_d2", 193 "mmpll_d6", 194 "mainpll_d3", 195 "mmpll_d7", 196 "univpll_d3", 197 "mmpll_d5_d2", 198 "mainpll_d2_d2", 199 "adsppll_d5", 200 "univpll_d3_d2" 201 }; 202 203 static const char * const dsp_parents[] = { 204 "clk26m", 205 "univpll_d3_d8", 206 "univpll_d3_d4", 207 "mainpll_d2_d4", 208 "univpll_d3_d2", 209 "mainpll_d2_d2", 210 "univpll_d2_d2", 211 "mainpll_d3", 212 "univpll_d3", 213 "mmpll_d7", 214 "mmpll_d6", 215 "adsppll_d5", 216 "tvdpll_ck", 217 "tvdpll_mainpll_d2_ck", 218 "univpll_d2", 219 "adsppll_d4" 220 }; 221 222 static const char * const dsp1_parents[] = { 223 "clk26m", 224 "univpll_d3_d8", 225 "univpll_d3_d4", 226 "mainpll_d2_d4", 227 "univpll_d3_d2", 228 "mainpll_d2_d2", 229 "univpll_d2_d2", 230 "mainpll_d3", 231 "univpll_d3", 232 "mmpll_d7", 233 "mmpll_d6", 234 "adsppll_d5", 235 "tvdpll_ck", 236 "tvdpll_mainpll_d2_ck", 237 "univpll_d2", 238 "adsppll_d4" 239 }; 240 241 static const char * const dsp2_parents[] = { 242 "clk26m", 243 "univpll_d3_d8", 244 "univpll_d3_d4", 245 "mainpll_d2_d4", 246 "univpll_d3_d2", 247 "mainpll_d2_d2", 248 "univpll_d2_d2", 249 "mainpll_d3", 250 "univpll_d3", 251 "mmpll_d7", 252 "mmpll_d6", 253 "adsppll_d5", 254 "tvdpll_ck", 255 "tvdpll_mainpll_d2_ck", 256 "univpll_d2", 257 "adsppll_d4" 258 }; 259 260 static const char * const dsp3_parents[] = { 261 "clk26m", 262 "univpll_d3_d8", 263 "mainpll_d2_d4", 264 "univpll_d3_d2", 265 "mainpll_d2_d2", 266 "univpll_d2_d2", 267 "mainpll_d3", 268 "univpll_d3", 269 "mmpll_d7", 270 "mmpll_d6", 271 "mainpll_d2", 272 "tvdpll_ck", 273 "tvdpll_mainpll_d2_ck", 274 "univpll_d2", 275 "adsppll_d4", 276 "mmpll_d4" 277 }; 278 279 static const char * const ipu_if_parents[] = { 280 "clk26m", 281 "univpll_d3_d8", 282 "univpll_d3_d4", 283 "mainpll_d2_d4", 284 "univpll_d3_d2", 285 "mainpll_d2_d2", 286 "univpll_d2_d2", 287 "mainpll_d3", 288 "univpll_d3", 289 "mmpll_d7", 290 "mmpll_d6", 291 "adsppll_d5", 292 "tvdpll_ck", 293 "tvdpll_mainpll_d2_ck", 294 "univpll_d2", 295 "adsppll_d4" 296 }; 297 298 static const char * const mfg_parents[] = { 299 "clk26m", 300 "mfgpll_ck", 301 "univpll_d3", 302 "mainpll_d5" 303 }; 304 305 static const char * const f52m_mfg_parents[] = { 306 "clk26m", 307 "univpll_d3_d2", 308 "univpll_d3_d4", 309 "univpll_d3_d8" 310 }; 311 312 static const char * const camtg_parents[] = { 313 "clk26m", 314 "univpll_192m_d8", 315 "univpll_d3_d8", 316 "univpll_192m_d4", 317 "univpll_d3_d16", 318 "csw_f26m_ck_d2", 319 "univpll_192m_d16", 320 "univpll_192m_d32" 321 }; 322 323 static const char * const camtg2_parents[] = { 324 "clk26m", 325 "univpll_192m_d8", 326 "univpll_d3_d8", 327 "univpll_192m_d4", 328 "univpll_d3_d16", 329 "csw_f26m_ck_d2", 330 "univpll_192m_d16", 331 "univpll_192m_d32" 332 }; 333 334 static const char * const camtg3_parents[] = { 335 "clk26m", 336 "univpll_192m_d8", 337 "univpll_d3_d8", 338 "univpll_192m_d4", 339 "univpll_d3_d16", 340 "csw_f26m_ck_d2", 341 "univpll_192m_d16", 342 "univpll_192m_d32" 343 }; 344 345 static const char * const camtg4_parents[] = { 346 "clk26m", 347 "univpll_192m_d8", 348 "univpll_d3_d8", 349 "univpll_192m_d4", 350 "univpll_d3_d16", 351 "csw_f26m_ck_d2", 352 "univpll_192m_d16", 353 "univpll_192m_d32" 354 }; 355 356 static const char * const uart_parents[] = { 357 "clk26m", 358 "univpll_d3_d8" 359 }; 360 361 static const char * const spi_parents[] = { 362 "clk26m", 363 "mainpll_d5_d2", 364 "mainpll_d3_d4", 365 "msdcpll_d4" 366 }; 367 368 static const char * const msdc50_hclk_parents[] = { 369 "clk26m", 370 "mainpll_d2_d2", 371 "mainpll_d3_d2" 372 }; 373 374 static const char * const msdc50_0_parents[] = { 375 "clk26m", 376 "msdcpll_ck", 377 "msdcpll_d2", 378 "univpll_d2_d4", 379 "mainpll_d3_d2", 380 "univpll_d2_d2" 381 }; 382 383 static const char * const msdc30_1_parents[] = { 384 "clk26m", 385 "univpll_d3_d2", 386 "mainpll_d3_d2", 387 "mainpll_d7", 388 "msdcpll_d2" 389 }; 390 391 static const char * const audio_parents[] = { 392 "clk26m", 393 "mainpll_d5_d4", 394 "mainpll_d7_d4", 395 "mainpll_d2_d16" 396 }; 397 398 static const char * const aud_intbus_parents[] = { 399 "clk26m", 400 "mainpll_d2_d4", 401 "mainpll_d7_d2" 402 }; 403 404 static const char * const fpwrap_ulposc_parents[] = { 405 "osc_d10", 406 "clk26m", 407 "osc_d4", 408 "osc_d8", 409 "osc_d16" 410 }; 411 412 static const char * const atb_parents[] = { 413 "clk26m", 414 "mainpll_d2_d2", 415 "mainpll_d5" 416 }; 417 418 static const char * const sspm_parents[] = { 419 "clk26m", 420 "univpll_d2_d4", 421 "mainpll_d2_d2", 422 "univpll_d2_d2", 423 "mainpll_d3" 424 }; 425 426 static const char * const dpi0_parents[] = { 427 "clk26m", 428 "tvdpll_d2", 429 "tvdpll_d4", 430 "tvdpll_d8", 431 "tvdpll_d16" 432 }; 433 434 static const char * const scam_parents[] = { 435 "clk26m", 436 "mainpll_d5_d2" 437 }; 438 439 static const char * const disppwm_parents[] = { 440 "clk26m", 441 "univpll_d3_d4", 442 "osc_d2", 443 "osc_d4", 444 "osc_d16" 445 }; 446 447 static const char * const usb_top_parents[] = { 448 "clk26m", 449 "univpll_d5_d4", 450 "univpll_d3_d4", 451 "univpll_d5_d2" 452 }; 453 454 static const char * const ssusb_top_xhci_parents[] = { 455 "clk26m", 456 "univpll_d5_d4", 457 "univpll_d3_d4", 458 "univpll_d5_d2" 459 }; 460 461 static const char * const spm_parents[] = { 462 "clk26m", 463 "osc_d8", 464 "mainpll_d2_d8" 465 }; 466 467 static const char * const i2c_parents[] = { 468 "clk26m", 469 "mainpll_d2_d8", 470 "univpll_d5_d2" 471 }; 472 473 static const char * const seninf_parents[] = { 474 "clk26m", 475 "univpll_d7", 476 "univpll_d3_d2", 477 "univpll_d2_d2", 478 "mainpll_d3", 479 "mmpll_d4_d2", 480 "mmpll_d7", 481 "mmpll_d6" 482 }; 483 484 static const char * const seninf1_parents[] = { 485 "clk26m", 486 "univpll_d7", 487 "univpll_d3_d2", 488 "univpll_d2_d2", 489 "mainpll_d3", 490 "mmpll_d4_d2", 491 "mmpll_d7", 492 "mmpll_d6" 493 }; 494 495 static const char * const seninf2_parents[] = { 496 "clk26m", 497 "univpll_d7", 498 "univpll_d3_d2", 499 "univpll_d2_d2", 500 "mainpll_d3", 501 "mmpll_d4_d2", 502 "mmpll_d7", 503 "mmpll_d6" 504 }; 505 506 static const char * const dxcc_parents[] = { 507 "clk26m", 508 "mainpll_d2_d2", 509 "mainpll_d2_d4", 510 "mainpll_d2_d8" 511 }; 512 513 static const char * const aud_engen1_parents[] = { 514 "clk26m", 515 "apll1_d2", 516 "apll1_d4", 517 "apll1_d8" 518 }; 519 520 static const char * const aud_engen2_parents[] = { 521 "clk26m", 522 "apll2_d2", 523 "apll2_d4", 524 "apll2_d8" 525 }; 526 527 static const char * const faes_ufsfde_parents[] = { 528 "clk26m", 529 "mainpll_d2", 530 "mainpll_d2_d2", 531 "mainpll_d3", 532 "mainpll_d2_d4", 533 "univpll_d3" 534 }; 535 536 static const char * const fufs_parents[] = { 537 "clk26m", 538 "mainpll_d2_d4", 539 "mainpll_d2_d8", 540 "mainpll_d2_d16" 541 }; 542 543 static const char * const aud_1_parents[] = { 544 "clk26m", 545 "apll1_ck" 546 }; 547 548 static const char * const aud_2_parents[] = { 549 "clk26m", 550 "apll2_ck" 551 }; 552 553 static const char * const adsp_parents[] = { 554 "clk26m", 555 "mainpll_d3", 556 "univpll_d2_d4", 557 "univpll_d2", 558 "mmpll_d4", 559 "adsppll_d4", 560 "adsppll_d6" 561 }; 562 563 static const char * const dpmaif_parents[] = { 564 "clk26m", 565 "univpll_d2_d4", 566 "mainpll_d3", 567 "mainpll_d2_d2", 568 "univpll_d2_d2", 569 "univpll_d3" 570 }; 571 572 static const char * const venc_parents[] = { 573 "clk26m", 574 "mmpll_d7", 575 "mainpll_d3", 576 "univpll_d2_d2", 577 "mainpll_d2_d2", 578 "univpll_d3", 579 "mmpll_d6", 580 "mainpll_d5", 581 "mainpll_d3_d2", 582 "mmpll_d4_d2", 583 "univpll_d2_d4", 584 "mmpll_d5", 585 "univpll_192m_d2" 586 587 }; 588 589 static const char * const vdec_parents[] = { 590 "clk26m", 591 "univpll_d2_d4", 592 "mainpll_d3", 593 "univpll_d2_d2", 594 "mainpll_d2_d2", 595 "univpll_d3", 596 "univpll_d5", 597 "univpll_d5_d2", 598 "mainpll_d2", 599 "univpll_d2", 600 "univpll_192m_d2" 601 }; 602 603 static const char * const camtm_parents[] = { 604 "clk26m", 605 "univpll_d7", 606 "univpll_d3_d2", 607 "univpll_d2_d2" 608 }; 609 610 static const char * const pwm_parents[] = { 611 "clk26m", 612 "univpll_d2_d8" 613 }; 614 615 static const char * const audio_h_parents[] = { 616 "clk26m", 617 "univpll_d7", 618 "apll1_ck", 619 "apll2_ck" 620 }; 621 622 static const char * const camtg5_parents[] = { 623 "clk26m", 624 "univpll_192m_d8", 625 "univpll_d3_d8", 626 "univpll_192m_d4", 627 "univpll_d3_d16", 628 "csw_f26m_ck_d2", 629 "univpll_192m_d16", 630 "univpll_192m_d32" 631 }; 632 633 /* 634 * CRITICAL CLOCK: 635 * axi_sel is the main bus clock of whole SOC. 636 * spm_sel is the clock of the always-on co-processor. 637 * sspm_sel is the clock of the always-on co-processor. 638 */ 639 static const struct mtk_mux top_muxes[] = { 640 /* CLK_CFG_0 */ 641 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents, 642 0x20, 0x24, 0x28, 0, 2, 7, 643 0x004, 0, CLK_IS_CRITICAL), 644 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents, 645 0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1), 646 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents, 647 0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2), 648 /* CLK_CFG_1 */ 649 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents, 650 0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4), 651 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents, 652 0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5), 653 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents, 654 0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6), 655 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents, 656 0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7), 657 /* CLK_CFG_2 */ 658 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents, 659 0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8), 660 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents, 661 0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9), 662 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents, 663 0x40, 0x44, 0x48, 16, 4, 23, 0x004, 10), 664 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "dsp2_sel", dsp2_parents, 665 0x40, 0x44, 0x48, 24, 4, 31, 0x004, 11), 666 /* CLK_CFG_3 */ 667 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "dsp3_sel", dsp3_parents, 668 0x50, 0x54, 0x58, 0, 4, 7, 0x004, 12), 669 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "ipu_if_sel", ipu_if_parents, 670 0x50, 0x54, 0x58, 8, 4, 15, 0x004, 13), 671 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "mfg_sel", mfg_parents, 672 0x50, 0x54, 0x58, 16, 2, 23, 0x004, 14), 673 MUX_GATE_CLR_SET_UPD(CLK_TOP_F52M_MFG, "f52m_mfg_sel", 674 f52m_mfg_parents, 0x50, 0x54, 0x58, 675 24, 2, 31, 0x004, 15), 676 /* CLK_CFG_4 */ 677 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "camtg_sel", camtg_parents, 678 0x60, 0x64, 0x68, 0, 3, 7, 0x004, 16), 679 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "camtg2_sel", camtg2_parents, 680 0x60, 0x64, 0x68, 8, 3, 15, 0x004, 17), 681 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "camtg3_sel", camtg3_parents, 682 0x60, 0x64, 0x68, 16, 3, 23, 0x004, 18), 683 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "camtg4_sel", camtg4_parents, 684 0x60, 0x64, 0x68, 24, 3, 31, 0x004, 19), 685 /* CLK_CFG_5 */ 686 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents, 687 0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20), 688 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents, 689 0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21), 690 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel", 691 msdc50_hclk_parents, 0x70, 0x74, 0x78, 692 16, 2, 23, 0x004, 22), 693 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel", 694 msdc50_0_parents, 0x70, 0x74, 0x78, 695 24, 3, 31, 0x004, 23), 696 /* CLK_CFG_6 */ 697 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel", 698 msdc30_1_parents, 0x80, 0x84, 0x88, 699 0, 3, 7, 0x004, 24), 700 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents, 701 0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25), 702 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel", 703 aud_intbus_parents, 0x80, 0x84, 0x88, 704 16, 2, 23, 0x004, 26), 705 MUX_GATE_CLR_SET_UPD(CLK_TOP_FPWRAP_ULPOSC, "fpwrap_ulposc_sel", 706 fpwrap_ulposc_parents, 0x80, 0x84, 0x88, 707 24, 3, 31, 0x004, 27), 708 /* CLK_CFG_7 */ 709 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "atb_sel", atb_parents, 710 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 28), 711 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents, 712 0x90, 0x94, 0x98, 8, 3, 15, 713 0x004, 29, CLK_IS_CRITICAL), 714 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents, 715 0x90, 0x94, 0x98, 16, 3, 23, 0x004, 30), 716 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents, 717 0x90, 0x94, 0x98, 24, 1, 31, 0x004, 0), 718 /* CLK_CFG_8 */ 719 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disppwm_sel", 720 disppwm_parents, 0xa0, 0xa4, 0xa8, 721 0, 3, 7, 0x008, 1), 722 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "usb_top_sel", 723 usb_top_parents, 0xa0, 0xa4, 0xa8, 724 8, 2, 15, 0x008, 2), 725 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", 726 ssusb_top_xhci_parents, 0xa0, 0xa4, 0xa8, 727 16, 2, 23, 0x008, 3), 728 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents, 729 0xa0, 0xa4, 0xa8, 24, 2, 31, 730 0x008, 4, CLK_IS_CRITICAL), 731 /* CLK_CFG_9 */ 732 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents, 733 0xb0, 0xb4, 0xb8, 0, 2, 7, 0x008, 5), 734 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "seninf_sel", seninf_parents, 735 0xb0, 0xb4, 0xb8, 8, 2, 15, 0x008, 6), 736 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "seninf1_sel", 737 seninf1_parents, 0xb0, 0xb4, 0xb8, 738 16, 2, 23, 0x008, 7), 739 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "seninf2_sel", 740 seninf2_parents, 0xb0, 0xb4, 0xb8, 741 24, 2, 31, 0x008, 8), 742 /* CLK_CFG_10 */ 743 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc_sel", dxcc_parents, 744 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 9), 745 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG1, "aud_eng1_sel", 746 aud_engen1_parents, 0xc0, 0xc4, 0xc8, 747 8, 2, 15, 0x008, 10), 748 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG2, "aud_eng2_sel", 749 aud_engen2_parents, 0xc0, 0xc4, 0xc8, 750 16, 2, 23, 0x008, 11), 751 MUX_GATE_CLR_SET_UPD(CLK_TOP_FAES_UFSFDE, "faes_ufsfde_sel", 752 faes_ufsfde_parents, 0xc0, 0xc4, 0xc8, 753 24, 3, 31, 754 0x008, 12), 755 /* CLK_CFG_11 */ 756 MUX_GATE_CLR_SET_UPD(CLK_TOP_FUFS, "fufs_sel", fufs_parents, 757 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 13), 758 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1_sel", aud_1_parents, 759 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x008, 14), 760 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2_sel", aud_2_parents, 761 0xd0, 0xd4, 0xd8, 16, 1, 23, 0x008, 15), 762 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "adsp_sel", adsp_parents, 763 0xd0, 0xd4, 0xd8, 24, 3, 31, 0x008, 16), 764 /* CLK_CFG_12 */ 765 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "dpmaif_sel", dpmaif_parents, 766 0xe0, 0xe4, 0xe8, 0, 3, 7, 0x008, 17), 767 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "venc_sel", venc_parents, 768 0xe0, 0xe4, 0xe8, 8, 4, 15, 0x008, 18), 769 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "vdec_sel", vdec_parents, 770 0xe0, 0xe4, 0xe8, 16, 4, 23, 0x008, 19), 771 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "camtm_sel", camtm_parents, 772 0xe0, 0xe4, 0xe8, 24, 2, 31, 0x004, 20), 773 /* CLK_CFG_13 */ 774 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "pwm_sel", pwm_parents, 775 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x008, 21), 776 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_H, "audio_h_sel", 777 audio_h_parents, 0xf0, 0xf4, 0xf8, 778 8, 2, 15, 0x008, 22), 779 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "camtg5_sel", camtg5_parents, 780 0xf0, 0xf4, 0xf8, 24, 3, 31, 0x008, 24), 781 }; 782 783 static const char * const i2s0_m_ck_parents[] = { 784 "aud_1_sel", 785 "aud_2_sel" 786 }; 787 788 static const char * const i2s1_m_ck_parents[] = { 789 "aud_1_sel", 790 "aud_2_sel" 791 }; 792 793 static const char * const i2s2_m_ck_parents[] = { 794 "aud_1_sel", 795 "aud_2_sel" 796 }; 797 798 static const char * const i2s3_m_ck_parents[] = { 799 "aud_1_sel", 800 "aud_2_sel" 801 }; 802 803 static const char * const i2s4_m_ck_parents[] = { 804 "aud_1_sel", 805 "aud_2_sel" 806 }; 807 808 static const char * const i2s5_m_ck_parents[] = { 809 "aud_1_sel", 810 "aud_2_sel" 811 }; 812 813 static const struct mtk_composite top_aud_muxes[] = { 814 MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 815 0x320, 8, 1), 816 MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 817 0x320, 9, 1), 818 MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 819 0x320, 10, 1), 820 MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 821 0x320, 11, 1), 822 MUX(CLK_TOP_I2S4_M_SEL, "i2s4_m_ck_sel", i2s4_m_ck_parents, 823 0x320, 12, 1), 824 MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents, 825 0x328, 20, 1), 826 }; 827 828 static struct mtk_composite top_aud_divs[] = { 829 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel", 830 0x320, 2, 0x324, 8, 0), 831 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel", 832 0x320, 3, 0x324, 8, 8), 833 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2s2_m_ck_sel", 834 0x320, 4, 0x324, 8, 16), 835 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2s3_m_ck_sel", 836 0x320, 5, 0x324, 8, 24), 837 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel", 838 0x320, 6, 0x328, 8, 0), 839 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 840 0x320, 7, 0x328, 8, 8), 841 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel", 842 0x328, 16, 0x328, 4, 28), 843 }; 844 845 static const struct mtk_gate_regs infra0_cg_regs = { 846 .set_ofs = 0x80, 847 .clr_ofs = 0x84, 848 .sta_ofs = 0x90, 849 }; 850 851 static const struct mtk_gate_regs infra1_cg_regs = { 852 .set_ofs = 0x88, 853 .clr_ofs = 0x8c, 854 .sta_ofs = 0x94, 855 }; 856 857 static const struct mtk_gate_regs infra2_cg_regs = { 858 .set_ofs = 0xa4, 859 .clr_ofs = 0xa8, 860 .sta_ofs = 0xac, 861 }; 862 863 static const struct mtk_gate_regs infra3_cg_regs = { 864 .set_ofs = 0xc0, 865 .clr_ofs = 0xc4, 866 .sta_ofs = 0xc8, 867 }; 868 869 #define GATE_INFRA0(_id, _name, _parent, _shift) \ 870 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \ 871 &mtk_clk_gate_ops_setclr) 872 #define GATE_INFRA1(_id, _name, _parent, _shift) \ 873 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \ 874 &mtk_clk_gate_ops_setclr) 875 #define GATE_INFRA2(_id, _name, _parent, _shift) \ 876 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 877 &mtk_clk_gate_ops_setclr) 878 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 879 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 880 &mtk_clk_gate_ops_setclr) 881 882 static const struct mtk_gate infra_clks[] = { 883 /* INFRA0 */ 884 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", 885 "axi_sel", 0), 886 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", 887 "axi_sel", 1), 888 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", 889 "axi_sel", 2), 890 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", 891 "axi_sel", 3), 892 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", 893 "axi_sel", 4), 894 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", 895 "f_f26m_ck", 5), 896 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", 897 "axi_sel", 6), 898 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", 899 "axi_sel", 8), 900 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", 901 "axi_sel", 9), 902 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", 903 "axi_sel", 10), 904 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", 905 "i2c_sel", 11), 906 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", 907 "i2c_sel", 12), 908 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", 909 "i2c_sel", 13), 910 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", 911 "i2c_sel", 14), 912 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", 913 "pwm_sel", 15), 914 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", 915 "pwm_sel", 16), 916 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", 917 "pwm_sel", 17), 918 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", 919 "pwm_sel", 18), 920 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", 921 "pwm_sel", 19), 922 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", 923 "pwm_sel", 21), 924 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", 925 "uart_sel", 22), 926 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", 927 "uart_sel", 23), 928 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", 929 "uart_sel", 24), 930 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", 931 "uart_sel", 25), 932 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", 933 "axi_sel", 27), 934 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", 935 "axi_sel", 28), 936 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", 937 "axi_sel", 31), 938 /* INFRA1 */ 939 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", 940 "spi_sel", 1), 941 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", 942 "msdc50_hclk_sel", 2), 943 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", 944 "axi_sel", 4), 945 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", 946 "axi_sel", 5), 947 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", 948 "msdc50_0_sel", 6), 949 GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", 950 "f_f26m_ck", 7), 951 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", 952 "axi_sel", 8), 953 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", 954 "axi_sel", 9), 955 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", 956 "f_f26m_ck", 10), 957 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", 958 "axi_sel", 11), 959 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", 960 "axi_sel", 12), 961 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", 962 "axi_sel", 13), 963 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", 964 "f_f26m_ck", 14), 965 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", 966 "msdc30_1_sel", 16), 967 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", 968 "msdc30_2_sel", 17), 969 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", 970 "axi_sel", 18), 971 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", 972 "axi_sel", 19), 973 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", 974 "axi_sel", 20), 975 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", 976 "axi_sel", 23), 977 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", 978 "axi_sel", 24), 979 GATE_INFRA1(CLK_INFRA_AUD, "infra_audio", 980 "axi_sel", 25), 981 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", 982 "axi_sel", 26), 983 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", 984 "dxcc_sel", 27), 985 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", 986 "dxcc_sel", 28), 987 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", 988 "axi_sel", 30), 989 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", 990 "f_f26m_ck", 31), 991 /* INFRA2 */ 992 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", 993 "f_f26m_ck", 0), 994 GATE_INFRA2(CLK_INFRA_USB, "infra_usb", 995 "usb_top_sel", 1), 996 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", 997 "axi_sel", 2), 998 GATE_INFRA2(CLK_INFRA_AUD_26M_BCLK, 999 "infracfg_ao_audio_26m_bclk", "f_f26m_ck", 4), 1000 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", 1001 "spi_sel", 6), 1002 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", 1003 "i2c_sel", 7), 1004 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", 1005 "f_f26m_ck", 8), 1006 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", 1007 "spi_sel", 9), 1008 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", 1009 "spi_sel", 10), 1010 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", 1011 "fufs_sel", 11), 1012 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", 1013 "fufs_sel", 12), 1014 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", 1015 "fufs_sel", 13), 1016 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", 1017 "axi_sel", 14), 1018 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", 1019 "axi_sel", 16), 1020 GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk", 1021 "axi_sel", 17), 1022 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", 1023 "i2c_sel", 18), 1024 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", 1025 "i2c_sel", 19), 1026 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", 1027 "i2c_sel", 20), 1028 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", 1029 "i2c_sel", 21), 1030 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", 1031 "i2c_sel", 22), 1032 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", 1033 "i2c_sel", 23), 1034 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", 1035 "i2c_sel", 24), 1036 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", 1037 "spi_sel", 25), 1038 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", 1039 "spi_sel", 26), 1040 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", 1041 "axi_sel", 27), 1042 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", 1043 "fufs_sel", 28), 1044 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", 1045 "faes_ufsfde_sel", 29), 1046 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", 1047 "fufs_sel", 30), 1048 GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci", 1049 "ssusb_top_xhci_sel", 31), 1050 /* INFRA3 */ 1051 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", 1052 "msdc50_0_sel", 0), 1053 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", 1054 "msdc50_0_sel", 1), 1055 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", 1056 "msdc50_0_sel", 2), 1057 GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self", 1058 "f_f26m_ck", 3), 1059 GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self", 1060 "f_f26m_ck", 4), 1061 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", 1062 "axi_sel", 5), 1063 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", 1064 "i2c_sel", 6), 1065 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", 1066 "msdc50_hclk_sel", 7), 1067 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", 1068 "msdc50_hclk_sel", 8), 1069 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", 1070 "axi_sel", 16), 1071 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", 1072 "axi_sel", 17), 1073 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", 1074 "axi_sel", 18), 1075 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", 1076 "axi_sel", 19), 1077 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", 1078 "f_f26m_ck", 20), 1079 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", 1080 "axi_sel", 21), 1081 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", 1082 "i2c_sel", 22), 1083 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", 1084 "i2c_sel", 23), 1085 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", 1086 "msdc50_0_sel", 24), 1087 GATE_INFRA3(CLK_INFRA_DPMAIF_CK, "infra_dpmaif", 1088 "dpmaif_sel", 26), 1089 GATE_INFRA3(CLK_INFRA_FADSP, "infra_fadsp", 1090 "adsp_sel", 27), 1091 GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap", 1092 "axi_sel", 28), 1093 GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md", 1094 "axi_sel", 29), 1095 GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6", 1096 "spi_sel", 30), 1097 GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7", 1098 "spi_sel", 31), 1099 }; 1100 1101 static const struct mtk_gate_regs apmixed_cg_regs = { 1102 .set_ofs = 0x20, 1103 .clr_ofs = 0x20, 1104 .sta_ofs = 0x20, 1105 }; 1106 1107 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ 1108 GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \ 1109 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags) 1110 1111 #define GATE_APMIXED(_id, _name, _parent, _shift) \ 1112 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0) 1113 1114 /* 1115 * CRITICAL CLOCK: 1116 * apmixed_appll26m is the toppest clock gate of all PLLs. 1117 */ 1118 static const struct mtk_gate apmixed_clks[] = { 1119 GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m", 1120 "f_f26m_ck", 4), 1121 GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL26M, "apmixed_appll26m", 1122 "f_f26m_ck", 5, CLK_IS_CRITICAL), 1123 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", 1124 "f_f26m_ck", 6), 1125 GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m", 1126 "f_f26m_ck", 7), 1127 GATE_APMIXED(CLK_APMIXED_MM_F26M, "apmixed_mmsys26m", 1128 "f_f26m_ck", 8), 1129 GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m", 1130 "f_f26m_ck", 9), 1131 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", 1132 "f_f26m_ck", 11), 1133 GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m", 1134 "f_f26m_ck", 13), 1135 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", 1136 "f_f26m_ck", 14), 1137 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", 1138 "f_f26m_ck", 16), 1139 GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", 1140 "f_f26m_ck", 17), 1141 }; 1142 1143 #define MT6779_PLL_FMAX (3800UL * MHZ) 1144 #define MT6779_PLL_FMIN (1500UL * MHZ) 1145 1146 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1147 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1148 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1149 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1150 _pcw_chg_reg, _div_table) { \ 1151 .id = _id, \ 1152 .name = _name, \ 1153 .reg = _reg, \ 1154 .pwr_reg = _pwr_reg, \ 1155 .en_mask = _en_mask, \ 1156 .flags = _flags, \ 1157 .rst_bar_mask = _rst_bar_mask, \ 1158 .fmax = MT6779_PLL_FMAX, \ 1159 .fmin = MT6779_PLL_FMIN, \ 1160 .pcwbits = _pcwbits, \ 1161 .pcwibits = _pcwibits, \ 1162 .pd_reg = _pd_reg, \ 1163 .pd_shift = _pd_shift, \ 1164 .tuner_reg = _tuner_reg, \ 1165 .tuner_en_reg = _tuner_en_reg, \ 1166 .tuner_en_bit = _tuner_en_bit, \ 1167 .pcw_reg = _pcw_reg, \ 1168 .pcw_shift = _pcw_shift, \ 1169 .pcw_chg_reg = _pcw_chg_reg, \ 1170 .div_table = _div_table, \ 1171 } 1172 1173 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1174 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1175 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1176 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1177 _pcw_chg_reg) \ 1178 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1179 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1180 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1181 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1182 _pcw_chg_reg, NULL) 1183 1184 static const struct mtk_pll_data plls[] = { 1185 PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0, 1186 PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0), 1187 PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, 0, 1188 PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0), 1189 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, 0, 1190 PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0), 1191 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0, 1192 (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0, 1193 0x0234, 0, 0), 1194 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, 0, 1195 (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24, 1196 0, 0, 0, 0x0244, 0, 0), 1197 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, 0, 1198 0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0), 1199 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, 0, 1200 0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0), 1201 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0, 1202 0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0), 1203 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, 0, 1204 (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24, 1205 0, 0, 0, 0x02b4, 0, 0), 1206 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, 0, 1207 (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24, 1208 0, 0, 0, 0x0284, 0, 0), 1209 PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, 0, 1210 0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0), 1211 PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, 0, 1212 0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4), 1213 }; 1214 1215 static int clk_mt6779_apmixed_probe(struct platform_device *pdev) 1216 { 1217 struct clk_hw_onecell_data *clk_data; 1218 struct device_node *node = pdev->dev.of_node; 1219 1220 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1221 1222 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1223 1224 mtk_clk_register_gates(node, apmixed_clks, 1225 ARRAY_SIZE(apmixed_clks), clk_data); 1226 1227 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1228 } 1229 1230 static int clk_mt6779_top_probe(struct platform_device *pdev) 1231 { 1232 void __iomem *base; 1233 struct clk_hw_onecell_data *clk_data; 1234 struct device_node *node = pdev->dev.of_node; 1235 1236 base = devm_platform_ioremap_resource(pdev, 0); 1237 if (IS_ERR(base)) 1238 return PTR_ERR(base); 1239 1240 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 1241 1242 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 1243 clk_data); 1244 1245 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); 1246 1247 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), 1248 node, &mt6779_clk_lock, clk_data); 1249 1250 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), 1251 base, &mt6779_clk_lock, clk_data); 1252 1253 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), 1254 base, &mt6779_clk_lock, clk_data); 1255 1256 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1257 } 1258 1259 static int clk_mt6779_infra_probe(struct platform_device *pdev) 1260 { 1261 struct clk_hw_onecell_data *clk_data; 1262 struct device_node *node = pdev->dev.of_node; 1263 1264 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1265 1266 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 1267 clk_data); 1268 1269 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1270 } 1271 1272 static const struct of_device_id of_match_clk_mt6779[] = { 1273 { 1274 .compatible = "mediatek,mt6779-apmixed", 1275 .data = clk_mt6779_apmixed_probe, 1276 }, { 1277 .compatible = "mediatek,mt6779-topckgen", 1278 .data = clk_mt6779_top_probe, 1279 }, { 1280 .compatible = "mediatek,mt6779-infracfg_ao", 1281 .data = clk_mt6779_infra_probe, 1282 }, { 1283 /* sentinel */ 1284 } 1285 }; 1286 1287 static int clk_mt6779_probe(struct platform_device *pdev) 1288 { 1289 int (*clk_probe)(struct platform_device *pdev); 1290 int r; 1291 1292 clk_probe = of_device_get_match_data(&pdev->dev); 1293 if (!clk_probe) 1294 return -EINVAL; 1295 1296 r = clk_probe(pdev); 1297 if (r) 1298 dev_err(&pdev->dev, 1299 "could not register clock provider: %s: %d\n", 1300 pdev->name, r); 1301 1302 return r; 1303 } 1304 1305 static struct platform_driver clk_mt6779_drv = { 1306 .probe = clk_mt6779_probe, 1307 .driver = { 1308 .name = "clk-mt6779", 1309 .of_match_table = of_match_clk_mt6779, 1310 }, 1311 }; 1312 1313 static int __init clk_mt6779_init(void) 1314 { 1315 return platform_driver_register(&clk_mt6779_drv); 1316 } 1317 1318 arch_initcall(clk_mt6779_init); 1319 MODULE_LICENSE("GPL"); 1320