1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Author: Wendell Lin <wendell.lin@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/of_device.h> 11 #include <linux/platform_device.h> 12 13 #include "clk-mtk.h" 14 #include "clk-mux.h" 15 #include "clk-gate.h" 16 17 #include <dt-bindings/clock/mt6779-clk.h> 18 19 static DEFINE_SPINLOCK(mt6779_clk_lock); 20 21 static const struct mtk_fixed_clk top_fixed_clks[] = { 22 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000), 23 }; 24 25 static const struct mtk_fixed_factor top_divs[] = { 26 FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2), 27 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2), 28 FACTOR(CLK_TOP_MAINPLL_CK, "mainpll_ck", "mainpll", 1, 1), 29 FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll_ck", 1, 2), 30 FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2), 31 FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4), 32 FACTOR(CLK_TOP_MAINPLL_D2_D8, "mainpll_d2_d8", "mainpll_d2", 1, 8), 33 FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16), 34 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3), 35 FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2), 36 FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4), 37 FACTOR(CLK_TOP_MAINPLL_D3_D8, "mainpll_d3_d8", "mainpll_d3", 1, 8), 38 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5), 39 FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2), 40 FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4), 41 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7), 42 FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2), 43 FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4), 44 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll", "univ2pll", 1, 2), 45 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 46 FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2), 47 FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4), 48 FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8), 49 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 50 FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2), 51 FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4), 52 FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8), 53 FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16), 54 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 55 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2), 56 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4), 57 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8), 58 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 59 FACTOR(CLK_TOP_UNIVP_192M_CK, "univpll_192m_ck", "univ2pll", 1, 13), 60 FACTOR(CLK_TOP_UNIVP_192M_D2, "univpll_192m_d2", "univpll_192m_ck", 61 1, 2), 62 FACTOR(CLK_TOP_UNIVP_192M_D4, "univpll_192m_d4", "univpll_192m_ck", 63 1, 4), 64 FACTOR(CLK_TOP_UNIVP_192M_D8, "univpll_192m_d8", "univpll_192m_ck", 65 1, 8), 66 FACTOR(CLK_TOP_UNIVP_192M_D16, "univpll_192m_d16", "univpll_192m_ck", 67 1, 16), 68 FACTOR(CLK_TOP_UNIVP_192M_D32, "univpll_192m_d32", "univpll_192m_ck", 69 1, 32), 70 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1), 71 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2), 72 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4), 73 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8), 74 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1), 75 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), 76 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), 77 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8), 78 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1), 79 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), 80 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 81 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8), 82 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16), 83 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1), 84 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), 85 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2), 86 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4), 87 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 88 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2), 89 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4), 90 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), 91 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 92 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1), 93 FACTOR(CLK_TOP_ADSPPLL_CK, "adsppll_ck", "adsppll", 1, 1), 94 FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4), 95 FACTOR(CLK_TOP_ADSPPLL_D5, "adsppll_d5", "adsppll", 1, 5), 96 FACTOR(CLK_TOP_ADSPPLL_D6, "adsppll_d6", "adsppll", 1, 6), 97 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1), 98 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 99 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 100 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8), 101 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16), 102 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1), 103 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2), 104 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4), 105 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8), 106 FACTOR(CLK_TOP_OSC_D10, "osc_d10", "osc", 1, 10), 107 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16), 108 FACTOR(CLK_TOP_AD_OSC2_CK, "ad_osc2_ck", "osc2", 1, 1), 109 FACTOR(CLK_TOP_OSC2_D2, "osc2_d2", "osc2", 1, 2), 110 FACTOR(CLK_TOP_OSC2_D3, "osc2_d3", "osc2", 1, 3), 111 FACTOR(CLK_TOP_TVDPLL_MAINPLL_D2_CK, "tvdpll_mainpll_d2_ck", 112 "tvdpll", 1, 1), 113 FACTOR(CLK_TOP_FMEM_466M_CK, "fmem_466m_ck", "fmem", 1, 1), 114 }; 115 116 static const char * const axi_parents[] = { 117 "clk26m", 118 "mainpll_d2_d4", 119 "mainpll_d7", 120 "osc_d4" 121 }; 122 123 static const char * const mm_parents[] = { 124 "clk26m", 125 "tvdpll_mainpll_d2_ck", 126 "mmpll_d7", 127 "mmpll_d5_d2", 128 "mainpll_d2_d2", 129 "mainpll_d3_d2" 130 }; 131 132 static const char * const scp_parents[] = { 133 "clk26m", 134 "univpll_d2_d8", 135 "mainpll_d2_d4", 136 "mainpll_d3", 137 "univpll_d3", 138 "ad_osc2_ck", 139 "osc2_d2", 140 "osc2_d3" 141 }; 142 143 static const char * const img_parents[] = { 144 "clk26m", 145 "mainpll_d2", 146 "mainpll_d2", 147 "univpll_d3", 148 "mainpll_d3", 149 "mmpll_d5_d2", 150 "tvdpll_mainpll_d2_ck", 151 "mainpll_d5" 152 }; 153 154 static const char * const ipe_parents[] = { 155 "clk26m", 156 "mainpll_d2", 157 "mmpll_d7", 158 "univpll_d3", 159 "mainpll_d3", 160 "mmpll_d5_d2", 161 "mainpll_d2_d2", 162 "mainpll_d5" 163 }; 164 165 static const char * const dpe_parents[] = { 166 "clk26m", 167 "mainpll_d2", 168 "mmpll_d7", 169 "univpll_d3", 170 "mainpll_d3", 171 "mmpll_d5_d2", 172 "mainpll_d2_d2", 173 "mainpll_d5" 174 }; 175 176 static const char * const cam_parents[] = { 177 "clk26m", 178 "mainpll_d2", 179 "mmpll_d6", 180 "mainpll_d3", 181 "mmpll_d7", 182 "univpll_d3", 183 "mmpll_d5_d2", 184 "adsppll_d5", 185 "tvdpll_mainpll_d2_ck", 186 "univpll_d3_d2" 187 }; 188 189 static const char * const ccu_parents[] = { 190 "clk26m", 191 "mainpll_d2", 192 "mmpll_d6", 193 "mainpll_d3", 194 "mmpll_d7", 195 "univpll_d3", 196 "mmpll_d5_d2", 197 "mainpll_d2_d2", 198 "adsppll_d5", 199 "univpll_d3_d2" 200 }; 201 202 static const char * const dsp_parents[] = { 203 "clk26m", 204 "univpll_d3_d8", 205 "univpll_d3_d4", 206 "mainpll_d2_d4", 207 "univpll_d3_d2", 208 "mainpll_d2_d2", 209 "univpll_d2_d2", 210 "mainpll_d3", 211 "univpll_d3", 212 "mmpll_d7", 213 "mmpll_d6", 214 "adsppll_d5", 215 "tvdpll_ck", 216 "tvdpll_mainpll_d2_ck", 217 "univpll_d2", 218 "adsppll_d4" 219 }; 220 221 static const char * const dsp1_parents[] = { 222 "clk26m", 223 "univpll_d3_d8", 224 "univpll_d3_d4", 225 "mainpll_d2_d4", 226 "univpll_d3_d2", 227 "mainpll_d2_d2", 228 "univpll_d2_d2", 229 "mainpll_d3", 230 "univpll_d3", 231 "mmpll_d7", 232 "mmpll_d6", 233 "adsppll_d5", 234 "tvdpll_ck", 235 "tvdpll_mainpll_d2_ck", 236 "univpll_d2", 237 "adsppll_d4" 238 }; 239 240 static const char * const dsp2_parents[] = { 241 "clk26m", 242 "univpll_d3_d8", 243 "univpll_d3_d4", 244 "mainpll_d2_d4", 245 "univpll_d3_d2", 246 "mainpll_d2_d2", 247 "univpll_d2_d2", 248 "mainpll_d3", 249 "univpll_d3", 250 "mmpll_d7", 251 "mmpll_d6", 252 "adsppll_d5", 253 "tvdpll_ck", 254 "tvdpll_mainpll_d2_ck", 255 "univpll_d2", 256 "adsppll_d4" 257 }; 258 259 static const char * const dsp3_parents[] = { 260 "clk26m", 261 "univpll_d3_d8", 262 "mainpll_d2_d4", 263 "univpll_d3_d2", 264 "mainpll_d2_d2", 265 "univpll_d2_d2", 266 "mainpll_d3", 267 "univpll_d3", 268 "mmpll_d7", 269 "mmpll_d6", 270 "mainpll_d2", 271 "tvdpll_ck", 272 "tvdpll_mainpll_d2_ck", 273 "univpll_d2", 274 "adsppll_d4", 275 "mmpll_d4" 276 }; 277 278 static const char * const ipu_if_parents[] = { 279 "clk26m", 280 "univpll_d3_d8", 281 "univpll_d3_d4", 282 "mainpll_d2_d4", 283 "univpll_d3_d2", 284 "mainpll_d2_d2", 285 "univpll_d2_d2", 286 "mainpll_d3", 287 "univpll_d3", 288 "mmpll_d7", 289 "mmpll_d6", 290 "adsppll_d5", 291 "tvdpll_ck", 292 "tvdpll_mainpll_d2_ck", 293 "univpll_d2", 294 "adsppll_d4" 295 }; 296 297 static const char * const mfg_parents[] = { 298 "clk26m", 299 "mfgpll_ck", 300 "univpll_d3", 301 "mainpll_d5" 302 }; 303 304 static const char * const f52m_mfg_parents[] = { 305 "clk26m", 306 "univpll_d3_d2", 307 "univpll_d3_d4", 308 "univpll_d3_d8" 309 }; 310 311 static const char * const camtg_parents[] = { 312 "clk26m", 313 "univpll_192m_d8", 314 "univpll_d3_d8", 315 "univpll_192m_d4", 316 "univpll_d3_d16", 317 "csw_f26m_ck_d2", 318 "univpll_192m_d16", 319 "univpll_192m_d32" 320 }; 321 322 static const char * const camtg2_parents[] = { 323 "clk26m", 324 "univpll_192m_d8", 325 "univpll_d3_d8", 326 "univpll_192m_d4", 327 "univpll_d3_d16", 328 "csw_f26m_ck_d2", 329 "univpll_192m_d16", 330 "univpll_192m_d32" 331 }; 332 333 static const char * const camtg3_parents[] = { 334 "clk26m", 335 "univpll_192m_d8", 336 "univpll_d3_d8", 337 "univpll_192m_d4", 338 "univpll_d3_d16", 339 "csw_f26m_ck_d2", 340 "univpll_192m_d16", 341 "univpll_192m_d32" 342 }; 343 344 static const char * const camtg4_parents[] = { 345 "clk26m", 346 "univpll_192m_d8", 347 "univpll_d3_d8", 348 "univpll_192m_d4", 349 "univpll_d3_d16", 350 "csw_f26m_ck_d2", 351 "univpll_192m_d16", 352 "univpll_192m_d32" 353 }; 354 355 static const char * const uart_parents[] = { 356 "clk26m", 357 "univpll_d3_d8" 358 }; 359 360 static const char * const spi_parents[] = { 361 "clk26m", 362 "mainpll_d5_d2", 363 "mainpll_d3_d4", 364 "msdcpll_d4" 365 }; 366 367 static const char * const msdc50_hclk_parents[] = { 368 "clk26m", 369 "mainpll_d2_d2", 370 "mainpll_d3_d2" 371 }; 372 373 static const char * const msdc50_0_parents[] = { 374 "clk26m", 375 "msdcpll_ck", 376 "msdcpll_d2", 377 "univpll_d2_d4", 378 "mainpll_d3_d2", 379 "univpll_d2_d2" 380 }; 381 382 static const char * const msdc30_1_parents[] = { 383 "clk26m", 384 "univpll_d3_d2", 385 "mainpll_d3_d2", 386 "mainpll_d7", 387 "msdcpll_d2" 388 }; 389 390 static const char * const audio_parents[] = { 391 "clk26m", 392 "mainpll_d5_d4", 393 "mainpll_d7_d4", 394 "mainpll_d2_d16" 395 }; 396 397 static const char * const aud_intbus_parents[] = { 398 "clk26m", 399 "mainpll_d2_d4", 400 "mainpll_d7_d2" 401 }; 402 403 static const char * const fpwrap_ulposc_parents[] = { 404 "osc_d10", 405 "clk26m", 406 "osc_d4", 407 "osc_d8", 408 "osc_d16" 409 }; 410 411 static const char * const atb_parents[] = { 412 "clk26m", 413 "mainpll_d2_d2", 414 "mainpll_d5" 415 }; 416 417 static const char * const sspm_parents[] = { 418 "clk26m", 419 "univpll_d2_d4", 420 "mainpll_d2_d2", 421 "univpll_d2_d2", 422 "mainpll_d3" 423 }; 424 425 static const char * const dpi0_parents[] = { 426 "clk26m", 427 "tvdpll_d2", 428 "tvdpll_d4", 429 "tvdpll_d8", 430 "tvdpll_d16" 431 }; 432 433 static const char * const scam_parents[] = { 434 "clk26m", 435 "mainpll_d5_d2" 436 }; 437 438 static const char * const disppwm_parents[] = { 439 "clk26m", 440 "univpll_d3_d4", 441 "osc_d2", 442 "osc_d4", 443 "osc_d16" 444 }; 445 446 static const char * const usb_top_parents[] = { 447 "clk26m", 448 "univpll_d5_d4", 449 "univpll_d3_d4", 450 "univpll_d5_d2" 451 }; 452 453 static const char * const ssusb_top_xhci_parents[] = { 454 "clk26m", 455 "univpll_d5_d4", 456 "univpll_d3_d4", 457 "univpll_d5_d2" 458 }; 459 460 static const char * const spm_parents[] = { 461 "clk26m", 462 "osc_d8", 463 "mainpll_d2_d8" 464 }; 465 466 static const char * const i2c_parents[] = { 467 "clk26m", 468 "mainpll_d2_d8", 469 "univpll_d5_d2" 470 }; 471 472 static const char * const seninf_parents[] = { 473 "clk26m", 474 "univpll_d7", 475 "univpll_d3_d2", 476 "univpll_d2_d2", 477 "mainpll_d3", 478 "mmpll_d4_d2", 479 "mmpll_d7", 480 "mmpll_d6" 481 }; 482 483 static const char * const seninf1_parents[] = { 484 "clk26m", 485 "univpll_d7", 486 "univpll_d3_d2", 487 "univpll_d2_d2", 488 "mainpll_d3", 489 "mmpll_d4_d2", 490 "mmpll_d7", 491 "mmpll_d6" 492 }; 493 494 static const char * const seninf2_parents[] = { 495 "clk26m", 496 "univpll_d7", 497 "univpll_d3_d2", 498 "univpll_d2_d2", 499 "mainpll_d3", 500 "mmpll_d4_d2", 501 "mmpll_d7", 502 "mmpll_d6" 503 }; 504 505 static const char * const dxcc_parents[] = { 506 "clk26m", 507 "mainpll_d2_d2", 508 "mainpll_d2_d4", 509 "mainpll_d2_d8" 510 }; 511 512 static const char * const aud_engen1_parents[] = { 513 "clk26m", 514 "apll1_d2", 515 "apll1_d4", 516 "apll1_d8" 517 }; 518 519 static const char * const aud_engen2_parents[] = { 520 "clk26m", 521 "apll2_d2", 522 "apll2_d4", 523 "apll2_d8" 524 }; 525 526 static const char * const faes_ufsfde_parents[] = { 527 "clk26m", 528 "mainpll_d2", 529 "mainpll_d2_d2", 530 "mainpll_d3", 531 "mainpll_d2_d4", 532 "univpll_d3" 533 }; 534 535 static const char * const fufs_parents[] = { 536 "clk26m", 537 "mainpll_d2_d4", 538 "mainpll_d2_d8", 539 "mainpll_d2_d16" 540 }; 541 542 static const char * const aud_1_parents[] = { 543 "clk26m", 544 "apll1_ck" 545 }; 546 547 static const char * const aud_2_parents[] = { 548 "clk26m", 549 "apll2_ck" 550 }; 551 552 static const char * const adsp_parents[] = { 553 "clk26m", 554 "mainpll_d3", 555 "univpll_d2_d4", 556 "univpll_d2", 557 "mmpll_d4", 558 "adsppll_d4", 559 "adsppll_d6" 560 }; 561 562 static const char * const dpmaif_parents[] = { 563 "clk26m", 564 "univpll_d2_d4", 565 "mainpll_d3", 566 "mainpll_d2_d2", 567 "univpll_d2_d2", 568 "univpll_d3" 569 }; 570 571 static const char * const venc_parents[] = { 572 "clk26m", 573 "mmpll_d7", 574 "mainpll_d3", 575 "univpll_d2_d2", 576 "mainpll_d2_d2", 577 "univpll_d3", 578 "mmpll_d6", 579 "mainpll_d5", 580 "mainpll_d3_d2", 581 "mmpll_d4_d2", 582 "univpll_d2_d4", 583 "mmpll_d5", 584 "univpll_192m_d2" 585 586 }; 587 588 static const char * const vdec_parents[] = { 589 "clk26m", 590 "univpll_d2_d4", 591 "mainpll_d3", 592 "univpll_d2_d2", 593 "mainpll_d2_d2", 594 "univpll_d3", 595 "univpll_d5", 596 "univpll_d5_d2", 597 "mainpll_d2", 598 "univpll_d2", 599 "univpll_192m_d2" 600 }; 601 602 static const char * const camtm_parents[] = { 603 "clk26m", 604 "univpll_d7", 605 "univpll_d3_d2", 606 "univpll_d2_d2" 607 }; 608 609 static const char * const pwm_parents[] = { 610 "clk26m", 611 "univpll_d2_d8" 612 }; 613 614 static const char * const audio_h_parents[] = { 615 "clk26m", 616 "univpll_d7", 617 "apll1_ck", 618 "apll2_ck" 619 }; 620 621 static const char * const camtg5_parents[] = { 622 "clk26m", 623 "univpll_192m_d8", 624 "univpll_d3_d8", 625 "univpll_192m_d4", 626 "univpll_d3_d16", 627 "csw_f26m_ck_d2", 628 "univpll_192m_d16", 629 "univpll_192m_d32" 630 }; 631 632 /* 633 * CRITICAL CLOCK: 634 * axi_sel is the main bus clock of whole SOC. 635 * spm_sel is the clock of the always-on co-processor. 636 * sspm_sel is the clock of the always-on co-processor. 637 */ 638 static const struct mtk_mux top_muxes[] = { 639 /* CLK_CFG_0 */ 640 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents, 641 0x20, 0x24, 0x28, 0, 2, 7, 642 0x004, 0, CLK_IS_CRITICAL), 643 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents, 644 0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1), 645 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents, 646 0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2), 647 /* CLK_CFG_1 */ 648 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents, 649 0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4), 650 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents, 651 0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5), 652 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents, 653 0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6), 654 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents, 655 0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7), 656 /* CLK_CFG_2 */ 657 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents, 658 0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8), 659 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents, 660 0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9), 661 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents, 662 0x40, 0x44, 0x48, 16, 4, 23, 0x004, 10), 663 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "dsp2_sel", dsp2_parents, 664 0x40, 0x44, 0x48, 24, 4, 31, 0x004, 11), 665 /* CLK_CFG_3 */ 666 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "dsp3_sel", dsp3_parents, 667 0x50, 0x54, 0x58, 0, 4, 7, 0x004, 12), 668 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "ipu_if_sel", ipu_if_parents, 669 0x50, 0x54, 0x58, 8, 4, 15, 0x004, 13), 670 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "mfg_sel", mfg_parents, 671 0x50, 0x54, 0x58, 16, 2, 23, 0x004, 14), 672 MUX_GATE_CLR_SET_UPD(CLK_TOP_F52M_MFG, "f52m_mfg_sel", 673 f52m_mfg_parents, 0x50, 0x54, 0x58, 674 24, 2, 31, 0x004, 15), 675 /* CLK_CFG_4 */ 676 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "camtg_sel", camtg_parents, 677 0x60, 0x64, 0x68, 0, 3, 7, 0x004, 16), 678 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "camtg2_sel", camtg2_parents, 679 0x60, 0x64, 0x68, 8, 3, 15, 0x004, 17), 680 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "camtg3_sel", camtg3_parents, 681 0x60, 0x64, 0x68, 16, 3, 23, 0x004, 18), 682 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "camtg4_sel", camtg4_parents, 683 0x60, 0x64, 0x68, 24, 3, 31, 0x004, 19), 684 /* CLK_CFG_5 */ 685 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents, 686 0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20), 687 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents, 688 0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21), 689 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel", 690 msdc50_hclk_parents, 0x70, 0x74, 0x78, 691 16, 2, 23, 0x004, 22), 692 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel", 693 msdc50_0_parents, 0x70, 0x74, 0x78, 694 24, 3, 31, 0x004, 23), 695 /* CLK_CFG_6 */ 696 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel", 697 msdc30_1_parents, 0x80, 0x84, 0x88, 698 0, 3, 7, 0x004, 24), 699 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents, 700 0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25), 701 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel", 702 aud_intbus_parents, 0x80, 0x84, 0x88, 703 16, 2, 23, 0x004, 26), 704 MUX_GATE_CLR_SET_UPD(CLK_TOP_FPWRAP_ULPOSC, "fpwrap_ulposc_sel", 705 fpwrap_ulposc_parents, 0x80, 0x84, 0x88, 706 24, 3, 31, 0x004, 27), 707 /* CLK_CFG_7 */ 708 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "atb_sel", atb_parents, 709 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 28), 710 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents, 711 0x90, 0x94, 0x98, 8, 3, 15, 712 0x004, 29, CLK_IS_CRITICAL), 713 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents, 714 0x90, 0x94, 0x98, 16, 3, 23, 0x004, 30), 715 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents, 716 0x90, 0x94, 0x98, 24, 1, 31, 0x004, 0), 717 /* CLK_CFG_8 */ 718 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disppwm_sel", 719 disppwm_parents, 0xa0, 0xa4, 0xa8, 720 0, 3, 7, 0x008, 1), 721 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "usb_top_sel", 722 usb_top_parents, 0xa0, 0xa4, 0xa8, 723 8, 2, 15, 0x008, 2), 724 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", 725 ssusb_top_xhci_parents, 0xa0, 0xa4, 0xa8, 726 16, 2, 23, 0x008, 3), 727 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents, 728 0xa0, 0xa4, 0xa8, 24, 2, 31, 729 0x008, 4, CLK_IS_CRITICAL), 730 /* CLK_CFG_9 */ 731 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents, 732 0xb0, 0xb4, 0xb8, 0, 2, 7, 0x008, 5), 733 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "seninf_sel", seninf_parents, 734 0xb0, 0xb4, 0xb8, 8, 2, 15, 0x008, 6), 735 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "seninf1_sel", 736 seninf1_parents, 0xb0, 0xb4, 0xb8, 737 16, 2, 23, 0x008, 7), 738 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "seninf2_sel", 739 seninf2_parents, 0xb0, 0xb4, 0xb8, 740 24, 2, 31, 0x008, 8), 741 /* CLK_CFG_10 */ 742 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc_sel", dxcc_parents, 743 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 9), 744 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG1, "aud_eng1_sel", 745 aud_engen1_parents, 0xc0, 0xc4, 0xc8, 746 8, 2, 15, 0x008, 10), 747 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG2, "aud_eng2_sel", 748 aud_engen2_parents, 0xc0, 0xc4, 0xc8, 749 16, 2, 23, 0x008, 11), 750 MUX_GATE_CLR_SET_UPD(CLK_TOP_FAES_UFSFDE, "faes_ufsfde_sel", 751 faes_ufsfde_parents, 0xc0, 0xc4, 0xc8, 752 24, 3, 31, 753 0x008, 12), 754 /* CLK_CFG_11 */ 755 MUX_GATE_CLR_SET_UPD(CLK_TOP_FUFS, "fufs_sel", fufs_parents, 756 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 13), 757 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1_sel", aud_1_parents, 758 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x008, 14), 759 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2_sel", aud_2_parents, 760 0xd0, 0xd4, 0xd8, 16, 1, 23, 0x008, 15), 761 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "adsp_sel", adsp_parents, 762 0xd0, 0xd4, 0xd8, 24, 3, 31, 0x008, 16), 763 /* CLK_CFG_12 */ 764 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "dpmaif_sel", dpmaif_parents, 765 0xe0, 0xe4, 0xe8, 0, 3, 7, 0x008, 17), 766 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "venc_sel", venc_parents, 767 0xe0, 0xe4, 0xe8, 8, 4, 15, 0x008, 18), 768 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "vdec_sel", vdec_parents, 769 0xe0, 0xe4, 0xe8, 16, 4, 23, 0x008, 19), 770 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "camtm_sel", camtm_parents, 771 0xe0, 0xe4, 0xe8, 24, 2, 31, 0x004, 20), 772 /* CLK_CFG_13 */ 773 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "pwm_sel", pwm_parents, 774 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x008, 21), 775 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_H, "audio_h_sel", 776 audio_h_parents, 0xf0, 0xf4, 0xf8, 777 8, 2, 15, 0x008, 22), 778 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "camtg5_sel", camtg5_parents, 779 0xf0, 0xf4, 0xf8, 24, 3, 31, 0x008, 24), 780 }; 781 782 static const char * const i2s0_m_ck_parents[] = { 783 "aud_1_sel", 784 "aud_2_sel" 785 }; 786 787 static const char * const i2s1_m_ck_parents[] = { 788 "aud_1_sel", 789 "aud_2_sel" 790 }; 791 792 static const char * const i2s2_m_ck_parents[] = { 793 "aud_1_sel", 794 "aud_2_sel" 795 }; 796 797 static const char * const i2s3_m_ck_parents[] = { 798 "aud_1_sel", 799 "aud_2_sel" 800 }; 801 802 static const char * const i2s4_m_ck_parents[] = { 803 "aud_1_sel", 804 "aud_2_sel" 805 }; 806 807 static const char * const i2s5_m_ck_parents[] = { 808 "aud_1_sel", 809 "aud_2_sel" 810 }; 811 812 static const struct mtk_composite top_aud_muxes[] = { 813 MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 814 0x320, 8, 1), 815 MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 816 0x320, 9, 1), 817 MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 818 0x320, 10, 1), 819 MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 820 0x320, 11, 1), 821 MUX(CLK_TOP_I2S4_M_SEL, "i2s4_m_ck_sel", i2s4_m_ck_parents, 822 0x320, 12, 1), 823 MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents, 824 0x328, 20, 1), 825 }; 826 827 static struct mtk_composite top_aud_divs[] = { 828 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel", 829 0x320, 2, 0x324, 8, 0), 830 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel", 831 0x320, 3, 0x324, 8, 8), 832 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2s2_m_ck_sel", 833 0x320, 4, 0x324, 8, 16), 834 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2s3_m_ck_sel", 835 0x320, 5, 0x324, 8, 24), 836 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel", 837 0x320, 6, 0x328, 8, 0), 838 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 839 0x320, 7, 0x328, 8, 8), 840 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel", 841 0x328, 16, 0x328, 4, 28), 842 }; 843 844 static const struct mtk_gate_regs infra0_cg_regs = { 845 .set_ofs = 0x80, 846 .clr_ofs = 0x84, 847 .sta_ofs = 0x90, 848 }; 849 850 static const struct mtk_gate_regs infra1_cg_regs = { 851 .set_ofs = 0x88, 852 .clr_ofs = 0x8c, 853 .sta_ofs = 0x94, 854 }; 855 856 static const struct mtk_gate_regs infra2_cg_regs = { 857 .set_ofs = 0xa4, 858 .clr_ofs = 0xa8, 859 .sta_ofs = 0xac, 860 }; 861 862 static const struct mtk_gate_regs infra3_cg_regs = { 863 .set_ofs = 0xc0, 864 .clr_ofs = 0xc4, 865 .sta_ofs = 0xc8, 866 }; 867 868 #define GATE_INFRA0(_id, _name, _parent, _shift) \ 869 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \ 870 &mtk_clk_gate_ops_setclr) 871 #define GATE_INFRA1(_id, _name, _parent, _shift) \ 872 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \ 873 &mtk_clk_gate_ops_setclr) 874 #define GATE_INFRA2(_id, _name, _parent, _shift) \ 875 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 876 &mtk_clk_gate_ops_setclr) 877 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 878 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 879 &mtk_clk_gate_ops_setclr) 880 881 static const struct mtk_gate infra_clks[] = { 882 /* INFRA0 */ 883 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", 884 "axi_sel", 0), 885 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", 886 "axi_sel", 1), 887 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", 888 "axi_sel", 2), 889 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", 890 "axi_sel", 3), 891 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", 892 "axi_sel", 4), 893 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", 894 "f_f26m_ck", 5), 895 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", 896 "axi_sel", 6), 897 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", 898 "axi_sel", 8), 899 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", 900 "axi_sel", 9), 901 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", 902 "axi_sel", 10), 903 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", 904 "i2c_sel", 11), 905 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", 906 "i2c_sel", 12), 907 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", 908 "i2c_sel", 13), 909 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", 910 "i2c_sel", 14), 911 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", 912 "pwm_sel", 15), 913 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", 914 "pwm_sel", 16), 915 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", 916 "pwm_sel", 17), 917 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", 918 "pwm_sel", 18), 919 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", 920 "pwm_sel", 19), 921 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", 922 "pwm_sel", 21), 923 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", 924 "uart_sel", 22), 925 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", 926 "uart_sel", 23), 927 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", 928 "uart_sel", 24), 929 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", 930 "uart_sel", 25), 931 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", 932 "axi_sel", 27), 933 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", 934 "axi_sel", 28), 935 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", 936 "axi_sel", 31), 937 /* INFRA1 */ 938 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", 939 "spi_sel", 1), 940 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", 941 "msdc50_hclk_sel", 2), 942 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", 943 "axi_sel", 4), 944 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", 945 "axi_sel", 5), 946 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", 947 "msdc50_0_sel", 6), 948 GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", 949 "f_f26m_ck", 7), 950 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", 951 "axi_sel", 8), 952 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", 953 "axi_sel", 9), 954 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", 955 "f_f26m_ck", 10), 956 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", 957 "axi_sel", 11), 958 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", 959 "axi_sel", 12), 960 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", 961 "axi_sel", 13), 962 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", 963 "f_f26m_ck", 14), 964 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", 965 "msdc30_1_sel", 16), 966 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", 967 "msdc30_2_sel", 17), 968 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", 969 "axi_sel", 18), 970 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", 971 "axi_sel", 19), 972 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", 973 "axi_sel", 20), 974 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", 975 "axi_sel", 23), 976 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", 977 "axi_sel", 24), 978 GATE_INFRA1(CLK_INFRA_AUD, "infra_audio", 979 "axi_sel", 25), 980 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", 981 "axi_sel", 26), 982 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", 983 "dxcc_sel", 27), 984 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", 985 "dxcc_sel", 28), 986 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", 987 "axi_sel", 30), 988 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", 989 "f_f26m_ck", 31), 990 /* INFRA2 */ 991 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", 992 "f_f26m_ck", 0), 993 GATE_INFRA2(CLK_INFRA_USB, "infra_usb", 994 "usb_top_sel", 1), 995 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", 996 "axi_sel", 2), 997 GATE_INFRA2(CLK_INFRA_AUD_26M_BCLK, 998 "infracfg_ao_audio_26m_bclk", "f_f26m_ck", 4), 999 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", 1000 "spi_sel", 6), 1001 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", 1002 "i2c_sel", 7), 1003 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", 1004 "f_f26m_ck", 8), 1005 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", 1006 "spi_sel", 9), 1007 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", 1008 "spi_sel", 10), 1009 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", 1010 "fufs_sel", 11), 1011 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", 1012 "fufs_sel", 12), 1013 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", 1014 "fufs_sel", 13), 1015 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", 1016 "axi_sel", 14), 1017 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", 1018 "axi_sel", 16), 1019 GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk", 1020 "axi_sel", 17), 1021 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", 1022 "i2c_sel", 18), 1023 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", 1024 "i2c_sel", 19), 1025 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", 1026 "i2c_sel", 20), 1027 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", 1028 "i2c_sel", 21), 1029 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", 1030 "i2c_sel", 22), 1031 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", 1032 "i2c_sel", 23), 1033 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", 1034 "i2c_sel", 24), 1035 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", 1036 "spi_sel", 25), 1037 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", 1038 "spi_sel", 26), 1039 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", 1040 "axi_sel", 27), 1041 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", 1042 "fufs_sel", 28), 1043 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", 1044 "faes_ufsfde_sel", 29), 1045 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", 1046 "fufs_sel", 30), 1047 GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci", 1048 "ssusb_top_xhci_sel", 31), 1049 /* INFRA3 */ 1050 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", 1051 "msdc50_0_sel", 0), 1052 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", 1053 "msdc50_0_sel", 1), 1054 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", 1055 "msdc50_0_sel", 2), 1056 GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self", 1057 "f_f26m_ck", 3), 1058 GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self", 1059 "f_f26m_ck", 4), 1060 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", 1061 "axi_sel", 5), 1062 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", 1063 "i2c_sel", 6), 1064 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", 1065 "msdc50_hclk_sel", 7), 1066 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", 1067 "msdc50_hclk_sel", 8), 1068 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", 1069 "axi_sel", 16), 1070 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", 1071 "axi_sel", 17), 1072 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", 1073 "axi_sel", 18), 1074 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", 1075 "axi_sel", 19), 1076 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", 1077 "f_f26m_ck", 20), 1078 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", 1079 "axi_sel", 21), 1080 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", 1081 "i2c_sel", 22), 1082 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", 1083 "i2c_sel", 23), 1084 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", 1085 "msdc50_0_sel", 24), 1086 GATE_INFRA3(CLK_INFRA_DPMAIF_CK, "infra_dpmaif", 1087 "dpmaif_sel", 26), 1088 GATE_INFRA3(CLK_INFRA_FADSP, "infra_fadsp", 1089 "adsp_sel", 27), 1090 GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap", 1091 "axi_sel", 28), 1092 GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md", 1093 "axi_sel", 29), 1094 GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6", 1095 "spi_sel", 30), 1096 GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7", 1097 "spi_sel", 31), 1098 }; 1099 1100 static const struct mtk_gate_regs apmixed_cg_regs = { 1101 .set_ofs = 0x20, 1102 .clr_ofs = 0x20, 1103 .sta_ofs = 0x20, 1104 }; 1105 1106 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ 1107 GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \ 1108 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags) 1109 1110 #define GATE_APMIXED(_id, _name, _parent, _shift) \ 1111 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0) 1112 1113 /* 1114 * CRITICAL CLOCK: 1115 * apmixed_appll26m is the toppest clock gate of all PLLs. 1116 */ 1117 static const struct mtk_gate apmixed_clks[] = { 1118 GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m", 1119 "f_f26m_ck", 4), 1120 GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL26M, "apmixed_appll26m", 1121 "f_f26m_ck", 5, CLK_IS_CRITICAL), 1122 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", 1123 "f_f26m_ck", 6), 1124 GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m", 1125 "f_f26m_ck", 7), 1126 GATE_APMIXED(CLK_APMIXED_MM_F26M, "apmixed_mmsys26m", 1127 "f_f26m_ck", 8), 1128 GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m", 1129 "f_f26m_ck", 9), 1130 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", 1131 "f_f26m_ck", 11), 1132 GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m", 1133 "f_f26m_ck", 13), 1134 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", 1135 "f_f26m_ck", 14), 1136 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", 1137 "f_f26m_ck", 16), 1138 GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", 1139 "f_f26m_ck", 17), 1140 }; 1141 1142 #define MT6779_PLL_FMAX (3800UL * MHZ) 1143 #define MT6779_PLL_FMIN (1500UL * MHZ) 1144 1145 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1146 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1147 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1148 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1149 _pcw_chg_reg, _div_table) { \ 1150 .id = _id, \ 1151 .name = _name, \ 1152 .reg = _reg, \ 1153 .pwr_reg = _pwr_reg, \ 1154 .en_mask = _en_mask, \ 1155 .flags = _flags, \ 1156 .rst_bar_mask = _rst_bar_mask, \ 1157 .fmax = MT6779_PLL_FMAX, \ 1158 .fmin = MT6779_PLL_FMIN, \ 1159 .pcwbits = _pcwbits, \ 1160 .pcwibits = _pcwibits, \ 1161 .pd_reg = _pd_reg, \ 1162 .pd_shift = _pd_shift, \ 1163 .tuner_reg = _tuner_reg, \ 1164 .tuner_en_reg = _tuner_en_reg, \ 1165 .tuner_en_bit = _tuner_en_bit, \ 1166 .pcw_reg = _pcw_reg, \ 1167 .pcw_shift = _pcw_shift, \ 1168 .pcw_chg_reg = _pcw_chg_reg, \ 1169 .div_table = _div_table, \ 1170 } 1171 1172 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1173 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1174 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1175 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1176 _pcw_chg_reg) \ 1177 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1178 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1179 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1180 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1181 _pcw_chg_reg, NULL) 1182 1183 static const struct mtk_pll_data plls[] = { 1184 PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0), 1185 PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0), 1186 PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0), 1187 PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0), 1188 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0), 1189 PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0), 1190 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0), 1191 (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0, 1192 0x0234, 0, 0), 1193 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0), 1194 (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24, 1195 0, 0, 0, 0x0244, 0, 0), 1196 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0), 1197 0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0), 1198 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0), 1199 0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0), 1200 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0), 1201 0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0), 1202 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0), 1203 (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24, 1204 0, 0, 0, 0x02b4, 0, 0), 1205 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0), 1206 (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24, 1207 0, 0, 0, 0x0284, 0, 0), 1208 PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0), 1209 0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0), 1210 PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0), 1211 0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4), 1212 }; 1213 1214 static int clk_mt6779_apmixed_probe(struct platform_device *pdev) 1215 { 1216 struct clk_onecell_data *clk_data; 1217 struct device_node *node = pdev->dev.of_node; 1218 1219 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1220 1221 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1222 1223 mtk_clk_register_gates(node, apmixed_clks, 1224 ARRAY_SIZE(apmixed_clks), clk_data); 1225 1226 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1227 } 1228 1229 static int clk_mt6779_top_probe(struct platform_device *pdev) 1230 { 1231 void __iomem *base; 1232 struct clk_onecell_data *clk_data; 1233 struct device_node *node = pdev->dev.of_node; 1234 1235 base = devm_platform_ioremap_resource(pdev, 0); 1236 if (IS_ERR(base)) 1237 return PTR_ERR(base); 1238 1239 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 1240 1241 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 1242 clk_data); 1243 1244 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); 1245 1246 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), 1247 node, &mt6779_clk_lock, clk_data); 1248 1249 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), 1250 base, &mt6779_clk_lock, clk_data); 1251 1252 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), 1253 base, &mt6779_clk_lock, clk_data); 1254 1255 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1256 } 1257 1258 static int clk_mt6779_infra_probe(struct platform_device *pdev) 1259 { 1260 struct clk_onecell_data *clk_data; 1261 struct device_node *node = pdev->dev.of_node; 1262 1263 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1264 1265 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 1266 clk_data); 1267 1268 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1269 } 1270 1271 static const struct of_device_id of_match_clk_mt6779[] = { 1272 { 1273 .compatible = "mediatek,mt6779-apmixed", 1274 .data = clk_mt6779_apmixed_probe, 1275 }, { 1276 .compatible = "mediatek,mt6779-topckgen", 1277 .data = clk_mt6779_top_probe, 1278 }, { 1279 .compatible = "mediatek,mt6779-infracfg_ao", 1280 .data = clk_mt6779_infra_probe, 1281 }, { 1282 /* sentinel */ 1283 } 1284 }; 1285 1286 static int clk_mt6779_probe(struct platform_device *pdev) 1287 { 1288 int (*clk_probe)(struct platform_device *pdev); 1289 int r; 1290 1291 clk_probe = of_device_get_match_data(&pdev->dev); 1292 if (!clk_probe) 1293 return -EINVAL; 1294 1295 r = clk_probe(pdev); 1296 if (r) 1297 dev_err(&pdev->dev, 1298 "could not register clock provider: %s: %d\n", 1299 pdev->name, r); 1300 1301 return r; 1302 } 1303 1304 static struct platform_driver clk_mt6779_drv = { 1305 .probe = clk_mt6779_probe, 1306 .driver = { 1307 .name = "clk-mt6779", 1308 .of_match_table = of_match_clk_mt6779, 1309 }, 1310 }; 1311 1312 static int __init clk_mt6779_init(void) 1313 { 1314 return platform_driver_register(&clk_mt6779_drv); 1315 } 1316 1317 arch_initcall(clk_mt6779_init); 1318 MODULE_LICENSE("GPL"); 1319