1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Author: Wendell Lin <wendell.lin@mediatek.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/platform_device.h> 9 #include <dt-bindings/clock/mt6779-clk.h> 10 11 #include "clk-mtk.h" 12 #include "clk-gate.h" 13 14 static const struct mtk_gate_regs mm0_cg_regs = { 15 .set_ofs = 0x0104, 16 .clr_ofs = 0x0108, 17 .sta_ofs = 0x0100, 18 }; 19 20 static const struct mtk_gate_regs mm1_cg_regs = { 21 .set_ofs = 0x0114, 22 .clr_ofs = 0x0118, 23 .sta_ofs = 0x0110, 24 }; 25 26 #define GATE_MM0(_id, _name, _parent, _shift) \ 27 GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \ 28 &mtk_clk_gate_ops_setclr) 29 #define GATE_MM1(_id, _name, _parent, _shift) \ 30 GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \ 31 &mtk_clk_gate_ops_setclr) 32 33 static const struct mtk_gate mm_clks[] = { 34 /* MM0 */ 35 GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), 36 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), 37 GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2), 38 GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3), 39 GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4), 40 GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5), 41 GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6), 42 GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7), 43 GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8), 44 GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9), 45 GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10), 46 GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11), 47 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12), 48 GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13), 49 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14), 50 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15), 51 GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16), 52 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17), 53 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 18), 54 GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19), 55 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20), 56 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21), 57 GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22), 58 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23), 59 GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24), 60 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25), 61 GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26), 62 GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27), 63 GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28), 64 GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29), 65 GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30), 66 GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31), 67 /* MM1 */ 68 GATE_MM1(CLK_MM_DSI0_MM_CK, "mm_dsi0_mmck", "mm_sel", 0), 69 GATE_MM1(CLK_MM_DSI0_IF_CK, "mm_dsi0_ifck", "mm_sel", 1), 70 GATE_MM1(CLK_MM_DPI_MM_CK, "mm_dpi_mmck", "mm_sel", 2), 71 GATE_MM1(CLK_MM_DPI_IF_CK, "mm_dpi_ifck", "dpi0_sel", 3), 72 GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4), 73 GATE_MM1(CLK_MM_MDP_DL_RX_CK, "mm_mdp_dl_rxck", "mm_sel", 5), 74 GATE_MM1(CLK_MM_IPU_DL_RX_CK, "mm_ipu_dl_rxck", "mm_sel", 6), 75 GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7), 76 GATE_MM1(CLK_MM_MM_R2Y, "mm_mmsys_r2y", "mm_sel", 8), 77 GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9), 78 GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10), 79 GATE_MM1(CLK_MM_MDP_HDR, "mm_mdp_hdr", "mm_sel", 11), 80 GATE_MM1(CLK_MM_DBI_MM_CK, "mm_dbi_mmck", "mm_sel", 12), 81 GATE_MM1(CLK_MM_DBI_IF_CK, "mm_dbi_ifck", "dpi0_sel", 13), 82 GATE_MM1(CLK_MM_DISP_POSTMASK0, "mm_disp_pm0", "mm_sel", 14), 83 GATE_MM1(CLK_MM_DISP_HRT_BW, "mm_disp_hrt_bw", "mm_sel", 15), 84 GATE_MM1(CLK_MM_DISP_OVL_FBDC, "mm_disp_ovl_fbdc", "mm_sel", 16), 85 }; 86 87 static int clk_mt6779_mm_probe(struct platform_device *pdev) 88 { 89 struct device *dev = &pdev->dev; 90 struct device_node *node = dev->parent->of_node; 91 struct clk_onecell_data *clk_data; 92 93 clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); 94 95 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), 96 clk_data); 97 98 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 99 } 100 101 static struct platform_driver clk_mt6779_mm_drv = { 102 .probe = clk_mt6779_mm_probe, 103 .driver = { 104 .name = "clk-mt6779-mm", 105 }, 106 }; 107 108 builtin_platform_driver(clk_mt6779_mm_drv); 109