1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2018 MediaTek Inc.
4  * Author: Owen Chen <owen.chen@mediatek.com>
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/platform_device.h>
9 
10 #include "clk-mtk.h"
11 #include "clk-gate.h"
12 
13 #include <dt-bindings/clock/mt6765-clk.h>
14 
15 static const struct mtk_gate_regs mipi0a_cg_regs = {
16 	.set_ofs = 0x80,
17 	.clr_ofs = 0x80,
18 	.sta_ofs = 0x80,
19 };
20 
21 #define GATE_MIPI0A(_id, _name, _parent, _shift) {	\
22 		.id = _id,				\
23 		.name = _name,				\
24 		.parent_name = _parent,			\
25 		.regs = &mipi0a_cg_regs,			\
26 		.shift = _shift,			\
27 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
28 	}
29 
30 static const struct mtk_gate mipi0a_clks[] = {
31 	GATE_MIPI0A(CLK_MIPI0A_CSR_CSI_EN_0A,
32 		    "mipi0a_csr_0a", "f_fseninf_ck", 1),
33 };
34 
35 static int clk_mt6765_mipi0a_probe(struct platform_device *pdev)
36 {
37 	struct clk_onecell_data *clk_data;
38 	int r;
39 	struct device_node *node = pdev->dev.of_node;
40 
41 	clk_data = mtk_alloc_clk_data(CLK_MIPI0A_NR_CLK);
42 
43 	mtk_clk_register_gates(node, mipi0a_clks,
44 			       ARRAY_SIZE(mipi0a_clks), clk_data);
45 
46 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
47 
48 	if (r)
49 		pr_err("%s(): could not register clock provider: %d\n",
50 		       __func__, r);
51 
52 	return r;
53 }
54 
55 static const struct of_device_id of_match_clk_mt6765_mipi0a[] = {
56 	{ .compatible = "mediatek,mt6765-mipi0a", },
57 	{}
58 };
59 
60 static struct platform_driver clk_mt6765_mipi0a_drv = {
61 	.probe = clk_mt6765_mipi0a_probe,
62 	.driver = {
63 		.name = "clk-mt6765-mipi0a",
64 		.of_match_table = of_match_clk_mt6765_mipi0a,
65 	},
66 };
67 
68 builtin_platform_driver(clk_mt6765_mipi0a_drv);
69