1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2017 MediaTek Inc.
4  * Author: Weiyi Lu <weiyi.lu@mediatek.com>
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/slab.h>
15 
16 #include "clk-gate.h"
17 #include "clk-pll.h"
18 #include "clk-mtk.h"
19 
20 #include <dt-bindings/clock/mt2712-clk.h>
21 
22 static DEFINE_SPINLOCK(mt2712_clk_lock);
23 
24 static const struct mtk_fixed_clk top_fixed_clks[] = {
25 	FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000),
26 	FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000),
27 	FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000),
28 	FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000),
29 	FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000),
30 	FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000),
31 	FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000),
32 	FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000),
33 	FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768),
34 	FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747),
35 	FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000),
36 	FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000),
37 };
38 
39 static const struct mtk_fixed_factor top_early_divs[] = {
40 	FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
41 		1),
42 	FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
43 		2),
44 };
45 
46 static const struct mtk_fixed_factor top_divs[] = {
47 	FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
48 		1),
49 	FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
50 		2),
51 	FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
52 		3),
53 	FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1,
54 		1),
55 	FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1,
56 		1),
57 	FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
58 		2),
59 	FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1,
60 		2),
61 	FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1,
62 		4),
63 	FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1,
64 		8),
65 	FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
66 		16),
67 	FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1,
68 		3),
69 	FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1,
70 		2),
71 	FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1,
72 		4),
73 	FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1,
74 		5),
75 	FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
76 		2),
77 	FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1,
78 		4),
79 	FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1,
80 		7),
81 	FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
82 		2),
83 	FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1,
84 		4),
85 	FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1,
86 		1),
87 	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
88 		7),
89 	FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1,
90 		26),
91 	FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1,
92 		52),
93 	FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1,
94 		104),
95 	FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1,
96 		208),
97 	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
98 		2),
99 	FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
100 		2),
101 	FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
102 		4),
103 	FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
104 		8),
105 	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
106 		3),
107 	FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1,
108 		2),
109 	FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
110 		4),
111 	FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1,
112 		8),
113 	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
114 		5),
115 	FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1,
116 		2),
117 	FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1,
118 		4),
119 	FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1,
120 		8),
121 	FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1,
122 		1),
123 	FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1,
124 		1),
125 	FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1,
126 		1),
127 	FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1,
128 		1),
129 	FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1,
130 		1),
131 	FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1,
132 		1),
133 	FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
134 		1),
135 	FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
136 		2),
137 	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
138 		4),
139 	FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
140 		8),
141 	FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1,
142 		16),
143 	FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1,
144 		1),
145 	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1,
146 		2),
147 	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1,
148 		4),
149 	FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1,
150 		8),
151 	FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1,
152 		16),
153 	FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1,
154 		1),
155 	FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1,
156 		2),
157 	FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1,
158 		4),
159 	FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1,
160 		8),
161 	FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1,
162 		1),
163 	FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1,
164 		2),
165 	FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1,
166 		4),
167 	FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1,
168 		8),
169 	FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1,
170 		1),
171 	FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1,
172 		1),
173 	FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1,
174 		1),
175 	FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1,
176 		2),
177 	FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1,
178 		1),
179 	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1,
180 		2),
181 	FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1,
182 		1),
183 	FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1,
184 		2),
185 	FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1,
186 		1),
187 	FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1,
188 		2),
189 	FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1,
190 		1),
191 	FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
192 		2),
193 	FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1,
194 		4),
195 	FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1,
196 		8),
197 	FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1,
198 		1),
199 	FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1,
200 		2),
201 	FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1,
202 		4),
203 	FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1,
204 		1),
205 	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
206 		2),
207 	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1,
208 		4),
209 	FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1,
210 		1),
211 	FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1,
212 		2),
213 	FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1,
214 		4),
215 	FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1,
216 		4),
217 	FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,
218 		3),
219 	FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1,
220 		3),
221 };
222 
223 static const char * const axi_parents[] = {
224 	"clk26m",
225 	"syspll1_d2",
226 	"syspll_d5",
227 	"syspll1_d4",
228 	"univpll_d5",
229 	"univpll2_d2",
230 	"msdcpll2_ck"
231 };
232 
233 static const char * const mem_parents[] = {
234 	"clk26m",
235 	"dmpll_ck"
236 };
237 
238 static const char * const mm_parents[] = {
239 	"clk26m",
240 	"vencpll_ck",
241 	"syspll_d3",
242 	"syspll1_d2",
243 	"syspll_d5",
244 	"syspll1_d4",
245 	"univpll1_d2",
246 	"univpll2_d2"
247 };
248 
249 static const char * const pwm_parents[] = {
250 	"clk26m",
251 	"univpll2_d4",
252 	"univpll3_d2",
253 	"univpll1_d4"
254 };
255 
256 static const char * const vdec_parents[] = {
257 	"clk26m",
258 	"vcodecpll_ck",
259 	"tvdpll_429m",
260 	"univpll_d3",
261 	"vencpll_ck",
262 	"syspll_d3",
263 	"univpll1_d2",
264 	"mmpll_d2",
265 	"syspll3_d2",
266 	"tvdpll_ck"
267 };
268 
269 static const char * const venc_parents[] = {
270 	"clk26m",
271 	"univpll1_d2",
272 	"mmpll_d2",
273 	"tvdpll_d2",
274 	"syspll1_d2",
275 	"univpll_d5",
276 	"vcodecpll_d2",
277 	"univpll2_d2",
278 	"syspll3_d2"
279 };
280 
281 static const char * const mfg_parents[] = {
282 	"clk26m",
283 	"mmpll_ck",
284 	"univpll_d3",
285 	"clk26m",
286 	"clk26m",
287 	"clk26m",
288 	"clk26m",
289 	"clk26m",
290 	"clk26m",
291 	"syspll_d3",
292 	"syspll1_d2",
293 	"syspll_d5",
294 	"univpll_d3",
295 	"univpll1_d2",
296 	"univpll_d5",
297 	"univpll2_d2"
298 };
299 
300 static const char * const camtg_parents[] = {
301 	"clk26m",
302 	"univpll_d52",
303 	"univpll_d208",
304 	"univpll_d104",
305 	"clk26m_d2",
306 	"univpll_d26",
307 	"univpll2_d8",
308 	"syspll3_d4",
309 	"syspll3_d2",
310 	"univpll1_d4",
311 	"univpll2_d2"
312 };
313 
314 static const char * const uart_parents[] = {
315 	"clk26m",
316 	"univpll2_d8"
317 };
318 
319 static const char * const spi_parents[] = {
320 	"clk26m",
321 	"univpll2_d4",
322 	"univpll1_d4",
323 	"univpll2_d2",
324 	"univpll3_d2",
325 	"univpll1_d8"
326 };
327 
328 static const char * const usb20_parents[] = {
329 	"clk26m",
330 	"univpll1_d8",
331 	"univpll3_d4"
332 };
333 
334 static const char * const usb30_parents[] = {
335 	"clk26m",
336 	"univpll3_d2",
337 	"univpll3_d4",
338 	"univpll2_d4"
339 };
340 
341 static const char * const msdc50_0_h_parents[] = {
342 	"clk26m",
343 	"syspll1_d2",
344 	"syspll2_d2",
345 	"syspll4_d2",
346 	"univpll_d5",
347 	"univpll1_d4"
348 };
349 
350 static const char * const msdc50_0_parents[] = {
351 	"clk26m",
352 	"msdcpll_ck",
353 	"msdcpll_d2",
354 	"univpll1_d4",
355 	"syspll2_d2",
356 	"msdcpll_d4",
357 	"vencpll_d2",
358 	"univpll1_d2",
359 	"msdcpll2_ck",
360 	"msdcpll2_d2",
361 	"msdcpll2_d4"
362 };
363 
364 static const char * const msdc30_1_parents[] = {
365 	"clk26m",
366 	"univpll2_d2",
367 	"msdcpll_d2",
368 	"univpll1_d4",
369 	"syspll2_d2",
370 	"univpll_d7",
371 	"vencpll_d2"
372 };
373 
374 static const char * const msdc30_3_parents[] = {
375 	"clk26m",
376 	"msdcpll2_ck",
377 	"msdcpll2_d2",
378 	"univpll2_d2",
379 	"msdcpll2_d4",
380 	"univpll1_d4",
381 	"syspll2_d2",
382 	"syspll_d7",
383 	"univpll_d7",
384 	"vencpll_d2",
385 	"msdcpll_ck",
386 	"msdcpll_d2",
387 	"msdcpll_d4"
388 };
389 
390 static const char * const audio_parents[] = {
391 	"clk26m",
392 	"syspll3_d4",
393 	"syspll4_d4",
394 	"syspll1_d16"
395 };
396 
397 static const char * const aud_intbus_parents[] = {
398 	"clk26m",
399 	"syspll1_d4",
400 	"syspll4_d2",
401 	"univpll3_d2",
402 	"univpll2_d8",
403 	"syspll3_d2",
404 	"syspll3_d4"
405 };
406 
407 static const char * const pmicspi_parents[] = {
408 	"clk26m",
409 	"syspll1_d8",
410 	"syspll3_d4",
411 	"syspll1_d16",
412 	"univpll3_d4",
413 	"univpll_d26",
414 	"syspll3_d4"
415 };
416 
417 static const char * const dpilvds1_parents[] = {
418 	"clk26m",
419 	"lvdspll2_ck",
420 	"lvdspll2_d2",
421 	"lvdspll2_d4",
422 	"lvdspll2_d8",
423 	"clkfpc"
424 };
425 
426 static const char * const atb_parents[] = {
427 	"clk26m",
428 	"syspll1_d2",
429 	"univpll_d5",
430 	"syspll_d5"
431 };
432 
433 static const char * const nr_parents[] = {
434 	"clk26m",
435 	"univpll1_d4",
436 	"syspll2_d2",
437 	"syspll1_d4",
438 	"univpll1_d8",
439 	"univpll3_d2",
440 	"univpll2_d2",
441 	"syspll_d5"
442 };
443 
444 static const char * const nfi2x_parents[] = {
445 	"clk26m",
446 	"syspll4_d4",
447 	"univpll3_d4",
448 	"univpll1_d8",
449 	"syspll2_d4",
450 	"univpll3_d2",
451 	"syspll_d7",
452 	"syspll2_d2",
453 	"univpll2_d2",
454 	"syspll_d5",
455 	"syspll1_d2"
456 };
457 
458 static const char * const irda_parents[] = {
459 	"clk26m",
460 	"univpll2_d4",
461 	"syspll2_d4",
462 	"univpll2_d8"
463 };
464 
465 static const char * const cci400_parents[] = {
466 	"clk26m",
467 	"vencpll_ck",
468 	"armca35pll_600m",
469 	"armca35pll_400m",
470 	"univpll_d2",
471 	"syspll_d2",
472 	"msdcpll_ck",
473 	"univpll_d3"
474 };
475 
476 static const char * const aud_1_parents[] = {
477 	"clk26m",
478 	"apll1_ck",
479 	"univpll2_d4",
480 	"univpll2_d8"
481 };
482 
483 static const char * const aud_2_parents[] = {
484 	"clk26m",
485 	"apll2_ck",
486 	"univpll2_d4",
487 	"univpll2_d8"
488 };
489 
490 static const char * const mem_mfg_parents[] = {
491 	"clk26m",
492 	"mmpll_ck",
493 	"univpll_d3"
494 };
495 
496 static const char * const axi_mfg_parents[] = {
497 	"clk26m",
498 	"axi_sel",
499 	"univpll_d5"
500 };
501 
502 static const char * const scam_parents[] = {
503 	"clk26m",
504 	"syspll3_d2",
505 	"univpll2_d4",
506 	"syspll2_d4"
507 };
508 
509 static const char * const nfiecc_parents[] = {
510 	"clk26m",
511 	"nfi2x_sel",
512 	"syspll_d7",
513 	"syspll2_d2",
514 	"univpll2_d2",
515 	"univpll_d5",
516 	"syspll1_d2"
517 };
518 
519 static const char * const pe2_mac_p0_parents[] = {
520 	"clk26m",
521 	"syspll1_d8",
522 	"syspll4_d2",
523 	"syspll2_d4",
524 	"univpll2_d4",
525 	"syspll3_d2"
526 };
527 
528 static const char * const dpilvds_parents[] = {
529 	"clk26m",
530 	"lvdspll_ck",
531 	"lvdspll_d2",
532 	"lvdspll_d4",
533 	"lvdspll_d8",
534 	"clkfpc"
535 };
536 
537 static const char * const hdcp_parents[] = {
538 	"clk26m",
539 	"syspll4_d2",
540 	"syspll3_d4",
541 	"univpll2_d4"
542 };
543 
544 static const char * const hdcp_24m_parents[] = {
545 	"clk26m",
546 	"univpll_d26",
547 	"univpll_d52",
548 	"univpll2_d8"
549 };
550 
551 static const char * const rtc_parents[] = {
552 	"clkrtc_int",
553 	"clkrtc_ext",
554 	"clk26m",
555 	"univpll3_d8"
556 };
557 
558 static const char * const spinor_parents[] = {
559 	"clk26m",
560 	"clk26m_d2",
561 	"syspll4_d4",
562 	"univpll2_d8",
563 	"univpll3_d4",
564 	"syspll4_d2",
565 	"syspll2_d4",
566 	"univpll2_d4",
567 	"etherpll_125m",
568 	"syspll1_d4"
569 };
570 
571 static const char * const apll_parents[] = {
572 	"clk26m",
573 	"apll1_ck",
574 	"apll1_d2",
575 	"apll1_d4",
576 	"apll1_d8",
577 	"apll1_d16",
578 	"apll2_ck",
579 	"apll2_d2",
580 	"apll2_d4",
581 	"apll2_d8",
582 	"apll2_d16",
583 	"clk26m",
584 	"clk26m"
585 };
586 
587 static const char * const a1sys_hp_parents[] = {
588 	"clk26m",
589 	"apll1_ck",
590 	"apll1_d2",
591 	"apll1_d4",
592 	"apll1_d8",
593 	"apll1_d3"
594 };
595 
596 static const char * const a2sys_hp_parents[] = {
597 	"clk26m",
598 	"apll2_ck",
599 	"apll2_d2",
600 	"apll2_d4",
601 	"apll2_d8",
602 	"apll2_d3"
603 };
604 
605 static const char * const asm_l_parents[] = {
606 	"clk26m",
607 	"univpll2_d4",
608 	"univpll2_d2",
609 	"syspll_d5"
610 };
611 
612 static const char * const i2so1_parents[] = {
613 	"clk26m",
614 	"apll1_ck",
615 	"apll2_ck"
616 };
617 
618 static const char * const ether_125m_parents[] = {
619 	"clk26m",
620 	"etherpll_125m",
621 	"univpll3_d2"
622 };
623 
624 static const char * const ether_50m_parents[] = {
625 	"clk26m",
626 	"etherpll_50m",
627 	"apll1_d3",
628 	"univpll3_d4"
629 };
630 
631 static const char * const jpgdec_parents[] = {
632 	"clk26m",
633 	"univpll_d3",
634 	"tvdpll_429m",
635 	"vencpll_ck",
636 	"syspll_d3",
637 	"vcodecpll_ck",
638 	"univpll1_d2",
639 	"armca35pll_400m",
640 	"tvdpll_429m_d2",
641 	"tvdpll_429m_d4"
642 };
643 
644 static const char * const spislv_parents[] = {
645 	"clk26m",
646 	"univpll2_d4",
647 	"univpll1_d4",
648 	"univpll2_d2",
649 	"univpll3_d2",
650 	"univpll1_d8",
651 	"univpll1_d2",
652 	"univpll_d5"
653 };
654 
655 static const char * const ether_parents[] = {
656 	"clk26m",
657 	"etherpll_50m",
658 	"univpll_d26"
659 };
660 
661 static const char * const di_parents[] = {
662 	"clk26m",
663 	"tvdpll_d2",
664 	"tvdpll_d4",
665 	"tvdpll_d8",
666 	"vencpll_ck",
667 	"vencpll_d2",
668 	"cvbs",
669 	"cvbs_d2"
670 };
671 
672 static const char * const tvd_parents[] = {
673 	"clk26m",
674 	"cvbs_d2",
675 	"univpll2_d8"
676 };
677 
678 static const char * const i2c_parents[] = {
679 	"clk26m",
680 	"univpll_d26",
681 	"univpll2_d4",
682 	"univpll3_d2",
683 	"univpll1_d4"
684 };
685 
686 static const char * const msdc0p_aes_parents[] = {
687 	"clk26m",
688 	"syspll_d2",
689 	"univpll_d3",
690 	"vcodecpll_ck"
691 };
692 
693 static const char * const cmsys_parents[] = {
694 	"clk26m",
695 	"univpll_d3",
696 	"syspll_d3",
697 	"syspll1_d2",
698 	"syspll2_d2"
699 };
700 
701 static const char * const gcpu_parents[] = {
702 	"clk26m",
703 	"syspll_d3",
704 	"syspll1_d2",
705 	"univpll1_d2",
706 	"univpll_d5",
707 	"univpll3_d2",
708 	"univpll_d3"
709 };
710 
711 static const char * const aud_apll1_parents[] = {
712 	"apll1",
713 	"clkaud_ext_i_1"
714 };
715 
716 static const char * const aud_apll2_parents[] = {
717 	"apll2",
718 	"clkaud_ext_i_2"
719 };
720 
721 static const char * const apll1_ref_parents[] = {
722 	"clkaud_ext_i_2",
723 	"clkaud_ext_i_1",
724 	"clki2si0_mck_i",
725 	"clki2si1_mck_i",
726 	"clki2si2_mck_i",
727 	"clktdmin_mclk_i",
728 	"clki2si2_mck_i",
729 	"clktdmin_mclk_i"
730 };
731 
732 static const char * const audull_vtx_parents[] = {
733 	"d2a_ulclk_6p5m",
734 	"clkaud_ext_i_0"
735 };
736 
737 static struct mtk_composite top_muxes[] = {
738 	/* CLK_CFG_0 */
739 	MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
740 		7, CLK_IS_CRITICAL),
741 	MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
742 		15, CLK_IS_CRITICAL),
743 	MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
744 		mm_parents, 0x040, 24, 3, 31),
745 	/* CLK_CFG_1 */
746 	MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
747 		pwm_parents, 0x050, 0, 2, 7),
748 	MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel",
749 		vdec_parents, 0x050, 8, 4, 15),
750 	MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",
751 		venc_parents, 0x050, 16, 4, 23),
752 	MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel",
753 		mfg_parents, 0x050, 24, 4, 31),
754 	/* CLK_CFG_2 */
755 	MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",
756 		camtg_parents, 0x060, 0, 4, 7),
757 	MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
758 		uart_parents, 0x060, 8, 1, 15),
759 	MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
760 		spi_parents, 0x060, 16, 3, 23),
761 	MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel",
762 		usb20_parents, 0x060, 24, 2, 31),
763 	/* CLK_CFG_3 */
764 	MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel",
765 		usb30_parents, 0x070, 0, 2, 7),
766 	MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
767 		msdc50_0_h_parents, 0x070, 8, 3, 15),
768 	MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
769 		msdc50_0_parents, 0x070, 16, 4, 23),
770 	MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
771 		msdc30_1_parents, 0x070, 24, 3, 31),
772 	/* CLK_CFG_4 */
773 	MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
774 		msdc30_1_parents, 0x080, 0, 3, 7),
775 	MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel",
776 		msdc30_3_parents, 0x080, 8, 4, 15),
777 	MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel",
778 		audio_parents, 0x080, 16, 2, 23),
779 	MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
780 		aud_intbus_parents, 0x080, 24, 3, 31),
781 	/* CLK_CFG_5 */
782 	MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel",
783 		pmicspi_parents, 0x090, 0, 3, 7),
784 	MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel",
785 		dpilvds1_parents, 0x090, 8, 3, 15),
786 	MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel",
787 		atb_parents, 0x090, 16, 2, 23),
788 	MUX_GATE(CLK_TOP_NR_SEL, "nr_sel",
789 		nr_parents, 0x090, 24, 3, 31),
790 	/* CLK_CFG_6 */
791 	MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel",
792 		nfi2x_parents, 0x0a0, 0, 4, 7),
793 	MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel",
794 		irda_parents, 0x0a0, 8, 2, 15),
795 	MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel",
796 		cci400_parents, 0x0a0, 16, 3, 23),
797 	MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel",
798 		aud_1_parents, 0x0a0, 24, 2, 31),
799 	/* CLK_CFG_7 */
800 	MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
801 		aud_2_parents, 0x0b0, 0, 2, 7),
802 	MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel",
803 		mem_mfg_parents, 0x0b0, 8, 2, 15),
804 	MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel",
805 		axi_mfg_parents, 0x0b0, 16, 2, 23),
806 	MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel",
807 		scam_parents, 0x0b0, 24, 2, 31),
808 	/* CLK_CFG_8 */
809 	MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel",
810 		nfiecc_parents, 0x0c0, 0, 3, 7),
811 	MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel",
812 		pe2_mac_p0_parents, 0x0c0, 8, 3, 15),
813 	MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel",
814 		pe2_mac_p0_parents, 0x0c0, 16, 3, 23),
815 	MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel",
816 		dpilvds_parents, 0x0c0, 24, 3, 31),
817 	/* CLK_CFG_9 */
818 	MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel",
819 		msdc50_0_h_parents, 0x0d0, 0, 3, 7),
820 	MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel",
821 		hdcp_parents, 0x0d0, 8, 2, 15),
822 	MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel",
823 		hdcp_24m_parents, 0x0d0, 16, 2, 23),
824 	MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2,
825 		31, CLK_IS_CRITICAL),
826 	/* CLK_CFG_10 */
827 	MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel",
828 		spinor_parents, 0x500, 0, 4, 7),
829 	MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel",
830 		apll_parents, 0x500, 8, 4, 15),
831 	MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel",
832 		apll_parents, 0x500, 16, 4, 23),
833 	MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
834 		a1sys_hp_parents, 0x500, 24, 3, 31),
835 	/* CLK_CFG_11 */
836 	MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel",
837 		a2sys_hp_parents, 0x510, 0, 3, 7),
838 	MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel",
839 		asm_l_parents, 0x510, 8, 2, 15),
840 	MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel",
841 		asm_l_parents, 0x510, 16, 2, 23),
842 	MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel",
843 		asm_l_parents, 0x510, 24, 2, 31),
844 	/* CLK_CFG_12 */
845 	MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel",
846 		i2so1_parents, 0x520, 0, 2, 7),
847 	MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel",
848 		i2so1_parents, 0x520, 8, 2, 15),
849 	MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel",
850 		i2so1_parents, 0x520, 16, 2, 23),
851 	MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel",
852 		i2so1_parents, 0x520, 24, 2, 31),
853 	/* CLK_CFG_13 */
854 	MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel",
855 		i2so1_parents, 0x530, 0, 2, 7),
856 	MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel",
857 		i2so1_parents, 0x530, 8, 2, 15),
858 	MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel",
859 		i2so1_parents, 0x530, 16, 2, 23),
860 	MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel",
861 		i2so1_parents, 0x530, 24, 2, 31),
862 	/* CLK_CFG_14 */
863 	MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel",
864 		ether_125m_parents, 0x540, 0, 2, 7),
865 	MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel",
866 		ether_50m_parents, 0x540, 8, 2, 15),
867 	MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel",
868 		jpgdec_parents, 0x540, 16, 4, 23),
869 	MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel",
870 		spislv_parents, 0x540, 24, 3, 31),
871 	/* CLK_CFG_15 */
872 	MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel",
873 		ether_parents, 0x550, 0, 2, 7),
874 	MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel",
875 		camtg_parents, 0x550, 8, 4, 15),
876 	MUX_GATE(CLK_TOP_DI_SEL, "di_sel",
877 		di_parents, 0x550, 16, 3, 23),
878 	MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel",
879 		tvd_parents, 0x550, 24, 2, 31),
880 	/* CLK_CFG_16 */
881 	MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel",
882 		i2c_parents, 0x560, 0, 3, 7),
883 	MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel",
884 		pwm_parents, 0x560, 8, 2, 15),
885 	MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel",
886 		msdc0p_aes_parents, 0x560, 16, 2, 23),
887 	MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel",
888 		cmsys_parents, 0x560, 24, 3, 31),
889 	/* CLK_CFG_17 */
890 	MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel",
891 		gcpu_parents, 0x570, 0, 3, 7),
892 	/* CLK_AUDDIV_4 */
893 	MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel",
894 		aud_apll1_parents, 0x134, 0, 1),
895 	MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel",
896 		aud_apll2_parents, 0x134, 1, 1),
897 	MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel",
898 		audull_vtx_parents, 0x134, 31, 1),
899 	MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel",
900 		apll1_ref_parents, 0x134, 4, 3),
901 	MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel",
902 		apll1_ref_parents, 0x134, 7, 3),
903 };
904 
905 static const char * const mcu_mp0_parents[] = {
906 	"clk26m",
907 	"armca35pll_ck",
908 	"f_mp0_pll1_ck",
909 	"f_mp0_pll2_ck"
910 };
911 
912 static const char * const mcu_mp2_parents[] = {
913 	"clk26m",
914 	"armca72pll_ck",
915 	"f_big_pll1_ck",
916 	"f_big_pll2_ck"
917 };
918 
919 static const char * const mcu_bus_parents[] = {
920 	"clk26m",
921 	"cci400_sel",
922 	"f_bus_pll1_ck",
923 	"f_bus_pll2_ck"
924 };
925 
926 static struct mtk_composite mcu_muxes[] = {
927 	/* mp0_pll_divider_cfg */
928 	MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0,
929 		9, 2, -1, CLK_IS_CRITICAL),
930 	/* mp2_pll_divider_cfg */
931 	MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8,
932 		9, 2, -1, CLK_IS_CRITICAL),
933 	/* bus_pll_divider_cfg */
934 	MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
935 		9, 2, -1, CLK_IS_CRITICAL),
936 };
937 
938 static const struct mtk_clk_divider top_adj_divs[] = {
939 	DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8),
940 	DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8),
941 	DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8),
942 	DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8),
943 	DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8),
944 	DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8),
945 	DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8),
946 	DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8),
947 };
948 
949 static const struct mtk_gate_regs top0_cg_regs = {
950 	.set_ofs = 0x120,
951 	.clr_ofs = 0x120,
952 	.sta_ofs = 0x120,
953 };
954 
955 static const struct mtk_gate_regs top1_cg_regs = {
956 	.set_ofs = 0x424,
957 	.clr_ofs = 0x424,
958 	.sta_ofs = 0x424,
959 };
960 
961 #define GATE_TOP0(_id, _name, _parent, _shift) {	\
962 		.id = _id,				\
963 		.name = _name,				\
964 		.parent_name = _parent,			\
965 		.regs = &top0_cg_regs,			\
966 		.shift = _shift,			\
967 		.ops = &mtk_clk_gate_ops_no_setclr,	\
968 	}
969 
970 #define GATE_TOP1(_id, _name, _parent, _shift) {	\
971 		.id = _id,				\
972 		.name = _name,				\
973 		.parent_name = _parent,			\
974 		.regs = &top1_cg_regs,			\
975 		.shift = _shift,			\
976 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
977 	}
978 
979 static const struct mtk_gate top_clks[] = {
980 	/* TOP0 */
981 	GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
982 	GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
983 	GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
984 	GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
985 	GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
986 	GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
987 	GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
988 	GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
989 	/* TOP1 */
990 	GATE_TOP1(CLK_TOP_NFI2X_EN, "nfi2x_en", "nfi2x_sel", 0),
991 	GATE_TOP1(CLK_TOP_NFIECC_EN, "nfiecc_en", "nfiecc_sel", 1),
992 	GATE_TOP1(CLK_TOP_NFI1X_CK_EN, "nfi1x_ck_en", "nfi2x_sel", 2),
993 };
994 
995 static const struct mtk_gate_regs infra_cg_regs = {
996 	.set_ofs = 0x40,
997 	.clr_ofs = 0x44,
998 	.sta_ofs = 0x48,
999 };
1000 
1001 #define GATE_INFRA(_id, _name, _parent, _shift) {	\
1002 		.id = _id,				\
1003 		.name = _name,				\
1004 		.parent_name = _parent,			\
1005 		.regs = &infra_cg_regs,			\
1006 		.shift = _shift,			\
1007 		.ops = &mtk_clk_gate_ops_setclr,	\
1008 	}
1009 
1010 static const struct mtk_gate infra_clks[] = {
1011 	GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
1012 	GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
1013 	GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
1014 	GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
1015 	GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24),
1016 	GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25),
1017 	GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26),
1018 };
1019 
1020 static const struct mtk_gate_regs peri0_cg_regs = {
1021 	.set_ofs = 0x8,
1022 	.clr_ofs = 0x10,
1023 	.sta_ofs = 0x18,
1024 };
1025 
1026 static const struct mtk_gate_regs peri1_cg_regs = {
1027 	.set_ofs = 0xc,
1028 	.clr_ofs = 0x14,
1029 	.sta_ofs = 0x1c,
1030 };
1031 
1032 static const struct mtk_gate_regs peri2_cg_regs = {
1033 	.set_ofs = 0x42c,
1034 	.clr_ofs = 0x42c,
1035 	.sta_ofs = 0x42c,
1036 };
1037 
1038 #define GATE_PERI0(_id, _name, _parent, _shift) {	\
1039 		.id = _id,				\
1040 		.name = _name,				\
1041 		.parent_name = _parent,			\
1042 		.regs = &peri0_cg_regs,			\
1043 		.shift = _shift,			\
1044 		.ops = &mtk_clk_gate_ops_setclr,	\
1045 	}
1046 
1047 #define GATE_PERI1(_id, _name, _parent, _shift) {	\
1048 		.id = _id,				\
1049 		.name = _name,				\
1050 		.parent_name = _parent,			\
1051 		.regs = &peri1_cg_regs,			\
1052 		.shift = _shift,			\
1053 		.ops = &mtk_clk_gate_ops_setclr,	\
1054 	}
1055 
1056 #define GATE_PERI2(_id, _name, _parent, _shift) {	\
1057 		.id = _id,				\
1058 		.name = _name,				\
1059 		.parent_name = _parent,			\
1060 		.regs = &peri2_cg_regs,			\
1061 		.shift = _shift,			\
1062 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
1063 	}
1064 
1065 static const struct mtk_gate peri_clks[] = {
1066 	/* PERI0 */
1067 	GATE_PERI0(CLK_PERI_NFI, "per_nfi",
1068 		"axi_sel", 0),
1069 	GATE_PERI0(CLK_PERI_THERM, "per_therm",
1070 		"axi_sel", 1),
1071 	GATE_PERI0(CLK_PERI_PWM0, "per_pwm0",
1072 		"pwm_sel", 2),
1073 	GATE_PERI0(CLK_PERI_PWM1, "per_pwm1",
1074 		"pwm_sel", 3),
1075 	GATE_PERI0(CLK_PERI_PWM2, "per_pwm2",
1076 		"pwm_sel", 4),
1077 	GATE_PERI0(CLK_PERI_PWM3, "per_pwm3",
1078 		"pwm_sel", 5),
1079 	GATE_PERI0(CLK_PERI_PWM4, "per_pwm4",
1080 		"pwm_sel", 6),
1081 	GATE_PERI0(CLK_PERI_PWM5, "per_pwm5",
1082 		"pwm_sel", 7),
1083 	GATE_PERI0(CLK_PERI_PWM6, "per_pwm6",
1084 		"pwm_sel", 8),
1085 	GATE_PERI0(CLK_PERI_PWM7, "per_pwm7",
1086 		"pwm_sel", 9),
1087 	GATE_PERI0(CLK_PERI_PWM, "per_pwm",
1088 		"pwm_sel", 10),
1089 	GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma",
1090 		"axi_sel", 13),
1091 	GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0",
1092 		"msdc50_0_sel", 14),
1093 	GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1",
1094 		"msdc30_1_sel", 15),
1095 	GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2",
1096 		"msdc30_2_sel", 16),
1097 	GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3",
1098 		"msdc30_3_sel", 17),
1099 	GATE_PERI0(CLK_PERI_UART0, "per_uart0",
1100 		"uart_sel", 20),
1101 	GATE_PERI0(CLK_PERI_UART1, "per_uart1",
1102 		"uart_sel", 21),
1103 	GATE_PERI0(CLK_PERI_UART2, "per_uart2",
1104 		"uart_sel", 22),
1105 	GATE_PERI0(CLK_PERI_UART3, "per_uart3",
1106 		"uart_sel", 23),
1107 	GATE_PERI0(CLK_PERI_I2C0, "per_i2c0",
1108 		"axi_sel", 24),
1109 	GATE_PERI0(CLK_PERI_I2C1, "per_i2c1",
1110 		"axi_sel", 25),
1111 	GATE_PERI0(CLK_PERI_I2C2, "per_i2c2",
1112 		"axi_sel", 26),
1113 	GATE_PERI0(CLK_PERI_I2C3, "per_i2c3",
1114 		"axi_sel", 27),
1115 	GATE_PERI0(CLK_PERI_I2C4, "per_i2c4",
1116 		"axi_sel", 28),
1117 	GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc",
1118 		"ltepll_fs26m", 29),
1119 	GATE_PERI0(CLK_PERI_SPI0, "per_spi0",
1120 		"spi_sel", 30),
1121 	/* PERI1 */
1122 	GATE_PERI1(CLK_PERI_SPI, "per_spi",
1123 		"spinor_sel", 1),
1124 	GATE_PERI1(CLK_PERI_I2C5, "per_i2c5",
1125 		"axi_sel", 3),
1126 	GATE_PERI1(CLK_PERI_SPI2, "per_spi2",
1127 		"spi_sel", 5),
1128 	GATE_PERI1(CLK_PERI_SPI3, "per_spi3",
1129 		"spi_sel", 6),
1130 	GATE_PERI1(CLK_PERI_SPI5, "per_spi5",
1131 		"spi_sel", 8),
1132 	GATE_PERI1(CLK_PERI_UART4, "per_uart4",
1133 		"uart_sel", 9),
1134 	GATE_PERI1(CLK_PERI_SFLASH, "per_sflash",
1135 		"uart_sel", 11),
1136 	GATE_PERI1(CLK_PERI_GMAC, "per_gmac",
1137 		"uart_sel", 12),
1138 	GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0",
1139 		"uart_sel", 14),
1140 	GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1",
1141 		"uart_sel", 15),
1142 	GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk",
1143 		"uart_sel", 16),
1144 	/* PERI2 */
1145 	GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en",
1146 		"msdc50_0_sel", 0),
1147 	GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en",
1148 		"msdc30_1_sel", 1),
1149 	GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en",
1150 		"msdc30_2_sel", 2),
1151 	GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en",
1152 		"msdc30_3_sel", 3),
1153 	GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h",
1154 		"msdc50_0_h_sel", 4),
1155 	GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h",
1156 		"msdc50_3_h_sel", 5),
1157 	GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q",
1158 		"axi_sel", 6),
1159 	GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q",
1160 		"mem_sel", 7),
1161 };
1162 
1163 #define MT2712_PLL_FMAX		(3000UL * MHZ)
1164 
1165 #define CON0_MT2712_RST_BAR	BIT(24)
1166 
1167 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
1168 			_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,	\
1169 			_tuner_en_bit, _pcw_reg, _pcw_shift,		\
1170 			_div_table) {					\
1171 		.id = _id,						\
1172 		.name = _name,						\
1173 		.reg = _reg,						\
1174 		.pwr_reg = _pwr_reg,					\
1175 		.en_mask = _en_mask,					\
1176 		.flags = _flags,					\
1177 		.rst_bar_mask = CON0_MT2712_RST_BAR,			\
1178 		.fmax = MT2712_PLL_FMAX,				\
1179 		.pcwbits = _pcwbits,					\
1180 		.pd_reg = _pd_reg,					\
1181 		.pd_shift = _pd_shift,					\
1182 		.tuner_reg = _tuner_reg,				\
1183 		.tuner_en_reg = _tuner_en_reg,				\
1184 		.tuner_en_bit = _tuner_en_bit,				\
1185 		.pcw_reg = _pcw_reg,					\
1186 		.pcw_shift = _pcw_shift,				\
1187 		.div_table = _div_table,				\
1188 	}
1189 
1190 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
1191 			_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,	\
1192 			_tuner_en_bit, _pcw_reg, _pcw_shift)		\
1193 		PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,	\
1194 			_pcwbits, _pd_reg, _pd_shift, _tuner_reg,	\
1195 			_tuner_en_reg, _tuner_en_bit, _pcw_reg,		\
1196 			_pcw_shift, NULL)
1197 
1198 static const struct mtk_pll_div_table armca35pll_div_table[] = {
1199 	{ .div = 0, .freq = MT2712_PLL_FMAX },
1200 	{ .div = 1, .freq = 1202500000 },
1201 	{ .div = 2, .freq = 500500000 },
1202 	{ .div = 3, .freq = 315250000 },
1203 	{ .div = 4, .freq = 157625000 },
1204 	{ } /* sentinel */
1205 };
1206 
1207 static const struct mtk_pll_div_table armca72pll_div_table[] = {
1208 	{ .div = 0, .freq = MT2712_PLL_FMAX },
1209 	{ .div = 1, .freq = 994500000 },
1210 	{ .div = 2, .freq = 520000000 },
1211 	{ .div = 3, .freq = 315250000 },
1212 	{ .div = 4, .freq = 157625000 },
1213 	{ } /* sentinel */
1214 };
1215 
1216 static const struct mtk_pll_div_table mmpll_div_table[] = {
1217 	{ .div = 0, .freq = MT2712_PLL_FMAX },
1218 	{ .div = 1, .freq = 1001000000 },
1219 	{ .div = 2, .freq = 601250000 },
1220 	{ .div = 3, .freq = 250250000 },
1221 	{ .div = 4, .freq = 125125000 },
1222 	{ } /* sentinel */
1223 };
1224 
1225 static const struct mtk_pll_data plls[] = {
1226 	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
1227 		HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
1228 	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
1229 		HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
1230 	PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,
1231 		0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
1232 	PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
1233 		0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
1234 	PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,
1235 		0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
1236 	PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,
1237 		0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
1238 	PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100,
1239 		0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
1240 	PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100,
1241 		0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
1242 	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
1243 		0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
1244 	PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100,
1245 		0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
1246 	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100,
1247 		0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
1248 	PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100,
1249 		0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
1250 		mmpll_div_table),
1251 	PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100,
1252 		HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
1253 		armca35pll_div_table),
1254 	PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100,
1255 		0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
1256 		armca72pll_div_table),
1257 	PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100,
1258 		0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
1259 };
1260 
1261 static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
1262 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
1263 
1264 static const struct mtk_clk_rst_desc clk_rst_desc[] = {
1265 	/* infra */
1266 	{
1267 		.version = MTK_RST_SIMPLE,
1268 		.rst_bank_ofs = infrasys_rst_ofs,
1269 		.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
1270 	},
1271 	/* peri */
1272 	{
1273 		.version = MTK_RST_SIMPLE,
1274 		.rst_bank_ofs = pericfg_rst_ofs,
1275 		.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
1276 	},
1277 };
1278 
1279 static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
1280 {
1281 	struct clk_hw_onecell_data *clk_data;
1282 	int r;
1283 	struct device_node *node = pdev->dev.of_node;
1284 
1285 	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1286 
1287 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1288 
1289 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1290 
1291 	if (r != 0)
1292 		pr_err("%s(): could not register clock provider: %d\n",
1293 			__func__, r);
1294 
1295 	return r;
1296 }
1297 
1298 static struct clk_hw_onecell_data *top_clk_data;
1299 
1300 static void clk_mt2712_top_init_early(struct device_node *node)
1301 {
1302 	int r, i;
1303 
1304 	if (!top_clk_data) {
1305 		top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1306 
1307 		for (i = 0; i < CLK_TOP_NR_CLK; i++)
1308 			top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
1309 	}
1310 
1311 	mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1312 			top_clk_data);
1313 
1314 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
1315 	if (r)
1316 		pr_err("%s(): could not register clock provider: %d\n",
1317 			__func__, r);
1318 }
1319 
1320 CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen",
1321 			clk_mt2712_top_init_early);
1322 
1323 static int clk_mt2712_top_probe(struct platform_device *pdev)
1324 {
1325 	int r, i;
1326 	struct device_node *node = pdev->dev.of_node;
1327 	void __iomem *base;
1328 
1329 	base = devm_platform_ioremap_resource(pdev, 0);
1330 	if (IS_ERR(base)) {
1331 		pr_err("%s(): ioremap failed\n", __func__);
1332 		return PTR_ERR(base);
1333 	}
1334 
1335 	if (!top_clk_data) {
1336 		top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1337 	} else {
1338 		for (i = 0; i < CLK_TOP_NR_CLK; i++) {
1339 			if (top_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
1340 				top_clk_data->hws[i] = ERR_PTR(-ENOENT);
1341 		}
1342 	}
1343 
1344 	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1345 			top_clk_data);
1346 	mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1347 			top_clk_data);
1348 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1349 	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
1350 			&mt2712_clk_lock, top_clk_data);
1351 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
1352 			&mt2712_clk_lock, top_clk_data);
1353 	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
1354 			top_clk_data);
1355 
1356 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
1357 
1358 	if (r != 0)
1359 		pr_err("%s(): could not register clock provider: %d\n",
1360 			__func__, r);
1361 
1362 	return r;
1363 }
1364 
1365 static int clk_mt2712_infra_probe(struct platform_device *pdev)
1366 {
1367 	struct clk_hw_onecell_data *clk_data;
1368 	int r;
1369 	struct device_node *node = pdev->dev.of_node;
1370 
1371 	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1372 
1373 	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1374 			clk_data);
1375 
1376 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1377 
1378 	if (r != 0)
1379 		pr_err("%s(): could not register clock provider: %d\n",
1380 			__func__, r);
1381 
1382 	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
1383 
1384 	return r;
1385 }
1386 
1387 static int clk_mt2712_peri_probe(struct platform_device *pdev)
1388 {
1389 	struct clk_hw_onecell_data *clk_data;
1390 	int r;
1391 	struct device_node *node = pdev->dev.of_node;
1392 
1393 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1394 
1395 	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
1396 			clk_data);
1397 
1398 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1399 
1400 	if (r != 0)
1401 		pr_err("%s(): could not register clock provider: %d\n",
1402 			__func__, r);
1403 
1404 	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
1405 
1406 	return r;
1407 }
1408 
1409 static int clk_mt2712_mcu_probe(struct platform_device *pdev)
1410 {
1411 	struct clk_hw_onecell_data *clk_data;
1412 	int r;
1413 	struct device_node *node = pdev->dev.of_node;
1414 	void __iomem *base;
1415 
1416 	base = devm_platform_ioremap_resource(pdev, 0);
1417 	if (IS_ERR(base)) {
1418 		pr_err("%s(): ioremap failed\n", __func__);
1419 		return PTR_ERR(base);
1420 	}
1421 
1422 	clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
1423 
1424 	mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
1425 			&mt2712_clk_lock, clk_data);
1426 
1427 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1428 
1429 	if (r != 0)
1430 		pr_err("%s(): could not register clock provider: %d\n",
1431 			__func__, r);
1432 
1433 	return r;
1434 }
1435 
1436 static const struct of_device_id of_match_clk_mt2712[] = {
1437 	{
1438 		.compatible = "mediatek,mt2712-apmixedsys",
1439 		.data = clk_mt2712_apmixed_probe,
1440 	}, {
1441 		.compatible = "mediatek,mt2712-topckgen",
1442 		.data = clk_mt2712_top_probe,
1443 	}, {
1444 		.compatible = "mediatek,mt2712-infracfg",
1445 		.data = clk_mt2712_infra_probe,
1446 	}, {
1447 		.compatible = "mediatek,mt2712-pericfg",
1448 		.data = clk_mt2712_peri_probe,
1449 	}, {
1450 		.compatible = "mediatek,mt2712-mcucfg",
1451 		.data = clk_mt2712_mcu_probe,
1452 	}, {
1453 		/* sentinel */
1454 	}
1455 };
1456 
1457 static int clk_mt2712_probe(struct platform_device *pdev)
1458 {
1459 	int (*clk_probe)(struct platform_device *);
1460 	int r;
1461 
1462 	clk_probe = of_device_get_match_data(&pdev->dev);
1463 	if (!clk_probe)
1464 		return -EINVAL;
1465 
1466 	r = clk_probe(pdev);
1467 	if (r != 0)
1468 		dev_err(&pdev->dev,
1469 			"could not register clock provider: %s: %d\n",
1470 			pdev->name, r);
1471 
1472 	return r;
1473 }
1474 
1475 static struct platform_driver clk_mt2712_drv = {
1476 	.probe = clk_mt2712_probe,
1477 	.driver = {
1478 		.name = "clk-mt2712",
1479 		.of_match_table = of_match_clk_mt2712,
1480 	},
1481 };
1482 
1483 static int __init clk_mt2712_init(void)
1484 {
1485 	return platform_driver_register(&clk_mt2712_drv);
1486 }
1487 
1488 arch_initcall(clk_mt2712_init);
1489