1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017 MediaTek Inc. 4 * Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/slab.h> 15 16 #include "clk-gate.h" 17 #include "clk-pll.h" 18 #include "clk-mtk.h" 19 20 #include <dt-bindings/clock/mt2712-clk.h> 21 22 static DEFINE_SPINLOCK(mt2712_clk_lock); 23 24 static const struct mtk_fixed_clk top_fixed_clks[] = { 25 FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000), 26 FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000), 27 FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000), 28 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000), 29 FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000), 30 FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000), 31 FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000), 32 FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000), 33 FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768), 34 FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747), 35 FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000), 36 FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000), 37 }; 38 39 static const struct mtk_fixed_factor top_divs[] = { 40 FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1, 41 1), 42 FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1, 43 2), 44 FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1, 45 1), 46 FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1, 47 2), 48 FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1, 49 3), 50 FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1, 51 1), 52 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 53 1), 54 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 55 2), 56 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 57 2), 58 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 59 4), 60 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 61 8), 62 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 63 16), 64 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1, 65 3), 66 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 67 2), 68 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 69 4), 70 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1, 71 5), 72 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 73 2), 74 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 75 4), 76 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1, 77 7), 78 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 79 2), 80 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 81 4), 82 FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 83 1), 84 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1, 85 7), 86 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1, 87 26), 88 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1, 89 52), 90 FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1, 91 104), 92 FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1, 93 208), 94 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 95 2), 96 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 97 2), 98 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 99 4), 100 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 101 8), 102 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1, 103 3), 104 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 105 2), 106 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 107 4), 108 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 109 8), 110 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1, 111 5), 112 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 113 2), 114 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 115 4), 116 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 117 8), 118 FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1, 119 1), 120 FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1, 121 1), 122 FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1, 123 1), 124 FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1, 125 1), 126 FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1, 127 1), 128 FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1, 129 1), 130 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 131 1), 132 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 133 2), 134 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 135 4), 136 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 137 8), 138 FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1, 139 16), 140 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 141 1), 142 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 143 2), 144 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 145 4), 146 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 147 8), 148 FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1, 149 16), 150 FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, 151 1), 152 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1, 153 2), 154 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1, 155 4), 156 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1, 157 8), 158 FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1, 159 1), 160 FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1, 161 2), 162 FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1, 163 4), 164 FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1, 165 8), 166 FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1, 167 1), 168 FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1, 169 1), 170 FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1, 171 1), 172 FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1, 173 2), 174 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 175 1), 176 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, 177 2), 178 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 179 1), 180 FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1, 181 2), 182 FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 183 1), 184 FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1, 185 2), 186 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 187 1), 188 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 189 2), 190 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 191 4), 192 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 193 8), 194 FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1, 195 1), 196 FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1, 197 2), 198 FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1, 199 4), 200 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 201 1), 202 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 203 2), 204 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 205 4), 206 FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 207 1), 208 FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1, 209 2), 210 FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1, 211 4), 212 FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1, 213 4), 214 FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1, 215 3), 216 FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1, 217 3), 218 }; 219 220 static const char * const axi_parents[] = { 221 "clk26m", 222 "syspll1_d2", 223 "syspll_d5", 224 "syspll1_d4", 225 "univpll_d5", 226 "univpll2_d2", 227 "msdcpll2_ck" 228 }; 229 230 static const char * const mem_parents[] = { 231 "clk26m", 232 "dmpll_ck" 233 }; 234 235 static const char * const mm_parents[] = { 236 "clk26m", 237 "vencpll_ck", 238 "syspll_d3", 239 "syspll1_d2", 240 "syspll_d5", 241 "syspll1_d4", 242 "univpll1_d2", 243 "univpll2_d2" 244 }; 245 246 static const char * const pwm_parents[] = { 247 "clk26m", 248 "univpll2_d4", 249 "univpll3_d2", 250 "univpll1_d4" 251 }; 252 253 static const char * const vdec_parents[] = { 254 "clk26m", 255 "vcodecpll_ck", 256 "tvdpll_429m", 257 "univpll_d3", 258 "vencpll_ck", 259 "syspll_d3", 260 "univpll1_d2", 261 "mmpll_d2", 262 "syspll3_d2", 263 "tvdpll_ck" 264 }; 265 266 static const char * const venc_parents[] = { 267 "clk26m", 268 "univpll1_d2", 269 "mmpll_d2", 270 "tvdpll_d2", 271 "syspll1_d2", 272 "univpll_d5", 273 "vcodecpll_d2", 274 "univpll2_d2", 275 "syspll3_d2" 276 }; 277 278 static const char * const mfg_parents[] = { 279 "clk26m", 280 "mmpll_ck", 281 "univpll_d3", 282 "clk26m", 283 "clk26m", 284 "clk26m", 285 "clk26m", 286 "clk26m", 287 "clk26m", 288 "syspll_d3", 289 "syspll1_d2", 290 "syspll_d5", 291 "univpll_d3", 292 "univpll1_d2", 293 "univpll_d5", 294 "univpll2_d2" 295 }; 296 297 static const char * const camtg_parents[] = { 298 "clk26m", 299 "univpll_d52", 300 "univpll_d208", 301 "univpll_d104", 302 "clk26m_d2", 303 "univpll_d26", 304 "univpll2_d8", 305 "syspll3_d4", 306 "syspll3_d2", 307 "univpll1_d4", 308 "univpll2_d2" 309 }; 310 311 static const char * const uart_parents[] = { 312 "clk26m", 313 "univpll2_d8" 314 }; 315 316 static const char * const spi_parents[] = { 317 "clk26m", 318 "univpll2_d4", 319 "univpll1_d4", 320 "univpll2_d2", 321 "univpll3_d2", 322 "univpll1_d8" 323 }; 324 325 static const char * const usb20_parents[] = { 326 "clk26m", 327 "univpll1_d8", 328 "univpll3_d4" 329 }; 330 331 static const char * const usb30_parents[] = { 332 "clk26m", 333 "univpll3_d2", 334 "univpll3_d4", 335 "univpll2_d4" 336 }; 337 338 static const char * const msdc50_0_h_parents[] = { 339 "clk26m", 340 "syspll1_d2", 341 "syspll2_d2", 342 "syspll4_d2", 343 "univpll_d5", 344 "univpll1_d4" 345 }; 346 347 static const char * const msdc50_0_parents[] = { 348 "clk26m", 349 "msdcpll_ck", 350 "msdcpll_d2", 351 "univpll1_d4", 352 "syspll2_d2", 353 "msdcpll_d4", 354 "vencpll_d2", 355 "univpll1_d2", 356 "msdcpll2_ck", 357 "msdcpll2_d2", 358 "msdcpll2_d4" 359 }; 360 361 static const char * const msdc30_1_parents[] = { 362 "clk26m", 363 "univpll2_d2", 364 "msdcpll_d2", 365 "univpll1_d4", 366 "syspll2_d2", 367 "univpll_d7", 368 "vencpll_d2" 369 }; 370 371 static const char * const msdc30_3_parents[] = { 372 "clk26m", 373 "msdcpll2_ck", 374 "msdcpll2_d2", 375 "univpll2_d2", 376 "msdcpll2_d4", 377 "univpll1_d4", 378 "syspll2_d2", 379 "syspll_d7", 380 "univpll_d7", 381 "vencpll_d2", 382 "msdcpll_ck", 383 "msdcpll_d2", 384 "msdcpll_d4" 385 }; 386 387 static const char * const audio_parents[] = { 388 "clk26m", 389 "syspll3_d4", 390 "syspll4_d4", 391 "syspll1_d16" 392 }; 393 394 static const char * const aud_intbus_parents[] = { 395 "clk26m", 396 "syspll1_d4", 397 "syspll4_d2", 398 "univpll3_d2", 399 "univpll2_d8", 400 "syspll3_d2", 401 "syspll3_d4" 402 }; 403 404 static const char * const pmicspi_parents[] = { 405 "clk26m", 406 "syspll1_d8", 407 "syspll3_d4", 408 "syspll1_d16", 409 "univpll3_d4", 410 "univpll_d26", 411 "syspll3_d4" 412 }; 413 414 static const char * const dpilvds1_parents[] = { 415 "clk26m", 416 "lvdspll2_ck", 417 "lvdspll2_d2", 418 "lvdspll2_d4", 419 "lvdspll2_d8", 420 "clkfpc" 421 }; 422 423 static const char * const atb_parents[] = { 424 "clk26m", 425 "syspll1_d2", 426 "univpll_d5", 427 "syspll_d5" 428 }; 429 430 static const char * const nr_parents[] = { 431 "clk26m", 432 "univpll1_d4", 433 "syspll2_d2", 434 "syspll1_d4", 435 "univpll1_d8", 436 "univpll3_d2", 437 "univpll2_d2", 438 "syspll_d5" 439 }; 440 441 static const char * const nfi2x_parents[] = { 442 "clk26m", 443 "syspll4_d4", 444 "univpll3_d4", 445 "univpll1_d8", 446 "syspll2_d4", 447 "univpll3_d2", 448 "syspll_d7", 449 "syspll2_d2", 450 "univpll2_d2", 451 "syspll_d5", 452 "syspll1_d2" 453 }; 454 455 static const char * const irda_parents[] = { 456 "clk26m", 457 "univpll2_d4", 458 "syspll2_d4", 459 "univpll2_d8" 460 }; 461 462 static const char * const cci400_parents[] = { 463 "clk26m", 464 "vencpll_ck", 465 "armca35pll_600m", 466 "armca35pll_400m", 467 "univpll_d2", 468 "syspll_d2", 469 "msdcpll_ck", 470 "univpll_d3" 471 }; 472 473 static const char * const aud_1_parents[] = { 474 "clk26m", 475 "apll1_ck", 476 "univpll2_d4", 477 "univpll2_d8" 478 }; 479 480 static const char * const aud_2_parents[] = { 481 "clk26m", 482 "apll2_ck", 483 "univpll2_d4", 484 "univpll2_d8" 485 }; 486 487 static const char * const mem_mfg_parents[] = { 488 "clk26m", 489 "mmpll_ck", 490 "univpll_d3" 491 }; 492 493 static const char * const axi_mfg_parents[] = { 494 "clk26m", 495 "axi_sel", 496 "univpll_d5" 497 }; 498 499 static const char * const scam_parents[] = { 500 "clk26m", 501 "syspll3_d2", 502 "univpll2_d4", 503 "syspll2_d4" 504 }; 505 506 static const char * const nfiecc_parents[] = { 507 "clk26m", 508 "nfi2x_sel", 509 "syspll_d7", 510 "syspll2_d2", 511 "univpll2_d2", 512 "univpll_d5", 513 "syspll1_d2" 514 }; 515 516 static const char * const pe2_mac_p0_parents[] = { 517 "clk26m", 518 "syspll1_d8", 519 "syspll4_d2", 520 "syspll2_d4", 521 "univpll2_d4", 522 "syspll3_d2" 523 }; 524 525 static const char * const dpilvds_parents[] = { 526 "clk26m", 527 "lvdspll_ck", 528 "lvdspll_d2", 529 "lvdspll_d4", 530 "lvdspll_d8", 531 "clkfpc" 532 }; 533 534 static const char * const hdcp_parents[] = { 535 "clk26m", 536 "syspll4_d2", 537 "syspll3_d4", 538 "univpll2_d4" 539 }; 540 541 static const char * const hdcp_24m_parents[] = { 542 "clk26m", 543 "univpll_d26", 544 "univpll_d52", 545 "univpll2_d8" 546 }; 547 548 static const char * const rtc_parents[] = { 549 "clkrtc_int", 550 "clkrtc_ext", 551 "clk26m", 552 "univpll3_d8" 553 }; 554 555 static const char * const spinor_parents[] = { 556 "clk26m", 557 "clk26m_d2", 558 "syspll4_d4", 559 "univpll2_d8", 560 "univpll3_d4", 561 "syspll4_d2", 562 "syspll2_d4", 563 "univpll2_d4", 564 "etherpll_125m", 565 "syspll1_d4" 566 }; 567 568 static const char * const apll_parents[] = { 569 "clk26m", 570 "apll1_ck", 571 "apll1_d2", 572 "apll1_d4", 573 "apll1_d8", 574 "apll1_d16", 575 "apll2_ck", 576 "apll2_d2", 577 "apll2_d4", 578 "apll2_d8", 579 "apll2_d16", 580 "clk26m", 581 "clk26m" 582 }; 583 584 static const char * const a1sys_hp_parents[] = { 585 "clk26m", 586 "apll1_ck", 587 "apll1_d2", 588 "apll1_d4", 589 "apll1_d8", 590 "apll1_d3" 591 }; 592 593 static const char * const a2sys_hp_parents[] = { 594 "clk26m", 595 "apll2_ck", 596 "apll2_d2", 597 "apll2_d4", 598 "apll2_d8", 599 "apll2_d3" 600 }; 601 602 static const char * const asm_l_parents[] = { 603 "clk26m", 604 "univpll2_d4", 605 "univpll2_d2", 606 "syspll_d5" 607 }; 608 609 static const char * const i2so1_parents[] = { 610 "clk26m", 611 "apll1_ck", 612 "apll2_ck" 613 }; 614 615 static const char * const ether_125m_parents[] = { 616 "clk26m", 617 "etherpll_125m", 618 "univpll3_d2" 619 }; 620 621 static const char * const ether_50m_parents[] = { 622 "clk26m", 623 "etherpll_50m", 624 "apll1_d3", 625 "univpll3_d4" 626 }; 627 628 static const char * const jpgdec_parents[] = { 629 "clk26m", 630 "univpll_d3", 631 "tvdpll_429m", 632 "vencpll_ck", 633 "syspll_d3", 634 "vcodecpll_ck", 635 "univpll1_d2", 636 "armca35pll_400m", 637 "tvdpll_429m_d2", 638 "tvdpll_429m_d4" 639 }; 640 641 static const char * const spislv_parents[] = { 642 "clk26m", 643 "univpll2_d4", 644 "univpll1_d4", 645 "univpll2_d2", 646 "univpll3_d2", 647 "univpll1_d8", 648 "univpll1_d2", 649 "univpll_d5" 650 }; 651 652 static const char * const ether_parents[] = { 653 "clk26m", 654 "etherpll_50m", 655 "univpll_d26" 656 }; 657 658 static const char * const di_parents[] = { 659 "clk26m", 660 "tvdpll_d2", 661 "tvdpll_d4", 662 "tvdpll_d8", 663 "vencpll_ck", 664 "vencpll_d2", 665 "cvbs", 666 "cvbs_d2" 667 }; 668 669 static const char * const tvd_parents[] = { 670 "clk26m", 671 "cvbs_d2", 672 "univpll2_d8" 673 }; 674 675 static const char * const i2c_parents[] = { 676 "clk26m", 677 "univpll_d26", 678 "univpll2_d4", 679 "univpll3_d2", 680 "univpll1_d4" 681 }; 682 683 static const char * const msdc0p_aes_parents[] = { 684 "clk26m", 685 "syspll_d2", 686 "univpll_d3", 687 "vcodecpll_ck" 688 }; 689 690 static const char * const cmsys_parents[] = { 691 "clk26m", 692 "univpll_d3", 693 "syspll_d3", 694 "syspll1_d2", 695 "syspll2_d2" 696 }; 697 698 static const char * const gcpu_parents[] = { 699 "clk26m", 700 "syspll_d3", 701 "syspll1_d2", 702 "univpll1_d2", 703 "univpll_d5", 704 "univpll3_d2", 705 "univpll_d3" 706 }; 707 708 static const char * const aud_apll1_parents[] = { 709 "apll1", 710 "clkaud_ext_i_1" 711 }; 712 713 static const char * const aud_apll2_parents[] = { 714 "apll2", 715 "clkaud_ext_i_2" 716 }; 717 718 static const char * const apll1_ref_parents[] = { 719 "clkaud_ext_i_2", 720 "clkaud_ext_i_1", 721 "clki2si0_mck_i", 722 "clki2si1_mck_i", 723 "clki2si2_mck_i", 724 "clktdmin_mclk_i", 725 "clki2si2_mck_i", 726 "clktdmin_mclk_i" 727 }; 728 729 static const char * const audull_vtx_parents[] = { 730 "d2a_ulclk_6p5m", 731 "clkaud_ext_i_0" 732 }; 733 734 static struct mtk_composite top_muxes[] = { 735 /* CLK_CFG_0 */ 736 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3, 737 7, CLK_IS_CRITICAL), 738 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1, 739 15, CLK_IS_CRITICAL), 740 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", 741 mm_parents, 0x040, 24, 3, 31), 742 /* CLK_CFG_1 */ 743 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", 744 pwm_parents, 0x050, 0, 2, 7), 745 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", 746 vdec_parents, 0x050, 8, 4, 15), 747 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", 748 venc_parents, 0x050, 16, 4, 23), 749 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", 750 mfg_parents, 0x050, 24, 4, 31), 751 /* CLK_CFG_2 */ 752 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", 753 camtg_parents, 0x060, 0, 4, 7), 754 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", 755 uart_parents, 0x060, 8, 1, 15), 756 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", 757 spi_parents, 0x060, 16, 3, 23), 758 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", 759 usb20_parents, 0x060, 24, 2, 31), 760 /* CLK_CFG_3 */ 761 MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", 762 usb30_parents, 0x070, 0, 2, 7), 763 MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel", 764 msdc50_0_h_parents, 0x070, 8, 3, 15), 765 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 766 msdc50_0_parents, 0x070, 16, 4, 23), 767 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 768 msdc30_1_parents, 0x070, 24, 3, 31), 769 /* CLK_CFG_4 */ 770 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", 771 msdc30_1_parents, 0x080, 0, 3, 7), 772 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", 773 msdc30_3_parents, 0x080, 8, 4, 15), 774 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", 775 audio_parents, 0x080, 16, 2, 23), 776 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", 777 aud_intbus_parents, 0x080, 24, 3, 31), 778 /* CLK_CFG_5 */ 779 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", 780 pmicspi_parents, 0x090, 0, 3, 7), 781 MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel", 782 dpilvds1_parents, 0x090, 8, 3, 15), 783 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", 784 atb_parents, 0x090, 16, 2, 23), 785 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", 786 nr_parents, 0x090, 24, 3, 31), 787 /* CLK_CFG_6 */ 788 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", 789 nfi2x_parents, 0x0a0, 0, 4, 7), 790 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", 791 irda_parents, 0x0a0, 8, 2, 15), 792 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", 793 cci400_parents, 0x0a0, 16, 3, 23), 794 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", 795 aud_1_parents, 0x0a0, 24, 2, 31), 796 /* CLK_CFG_7 */ 797 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", 798 aud_2_parents, 0x0b0, 0, 2, 7), 799 MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel", 800 mem_mfg_parents, 0x0b0, 8, 2, 15), 801 MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel", 802 axi_mfg_parents, 0x0b0, 16, 2, 23), 803 MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", 804 scam_parents, 0x0b0, 24, 2, 31), 805 /* CLK_CFG_8 */ 806 MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel", 807 nfiecc_parents, 0x0c0, 0, 3, 7), 808 MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel", 809 pe2_mac_p0_parents, 0x0c0, 8, 3, 15), 810 MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel", 811 pe2_mac_p0_parents, 0x0c0, 16, 3, 23), 812 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", 813 dpilvds_parents, 0x0c0, 24, 3, 31), 814 /* CLK_CFG_9 */ 815 MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel", 816 msdc50_0_h_parents, 0x0d0, 0, 3, 7), 817 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", 818 hdcp_parents, 0x0d0, 8, 2, 15), 819 MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", 820 hdcp_24m_parents, 0x0d0, 16, 2, 23), 821 MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2, 822 31, CLK_IS_CRITICAL), 823 /* CLK_CFG_10 */ 824 MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel", 825 spinor_parents, 0x500, 0, 4, 7), 826 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", 827 apll_parents, 0x500, 8, 4, 15), 828 MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel", 829 apll_parents, 0x500, 16, 4, 23), 830 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", 831 a1sys_hp_parents, 0x500, 24, 3, 31), 832 /* CLK_CFG_11 */ 833 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", 834 a2sys_hp_parents, 0x510, 0, 3, 7), 835 MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", 836 asm_l_parents, 0x510, 8, 2, 15), 837 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", 838 asm_l_parents, 0x510, 16, 2, 23), 839 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", 840 asm_l_parents, 0x510, 24, 2, 31), 841 /* CLK_CFG_12 */ 842 MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel", 843 i2so1_parents, 0x520, 0, 2, 7), 844 MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel", 845 i2so1_parents, 0x520, 8, 2, 15), 846 MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel", 847 i2so1_parents, 0x520, 16, 2, 23), 848 MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel", 849 i2so1_parents, 0x520, 24, 2, 31), 850 /* CLK_CFG_13 */ 851 MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel", 852 i2so1_parents, 0x530, 0, 2, 7), 853 MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel", 854 i2so1_parents, 0x530, 8, 2, 15), 855 MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel", 856 i2so1_parents, 0x530, 16, 2, 23), 857 MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel", 858 i2so1_parents, 0x530, 24, 2, 31), 859 /* CLK_CFG_14 */ 860 MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel", 861 ether_125m_parents, 0x540, 0, 2, 7), 862 MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel", 863 ether_50m_parents, 0x540, 8, 2, 15), 864 MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel", 865 jpgdec_parents, 0x540, 16, 4, 23), 866 MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel", 867 spislv_parents, 0x540, 24, 3, 31), 868 /* CLK_CFG_15 */ 869 MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel", 870 ether_parents, 0x550, 0, 2, 7), 871 MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel", 872 camtg_parents, 0x550, 8, 4, 15), 873 MUX_GATE(CLK_TOP_DI_SEL, "di_sel", 874 di_parents, 0x550, 16, 3, 23), 875 MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel", 876 tvd_parents, 0x550, 24, 2, 31), 877 /* CLK_CFG_16 */ 878 MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel", 879 i2c_parents, 0x560, 0, 3, 7), 880 MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel", 881 pwm_parents, 0x560, 8, 2, 15), 882 MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel", 883 msdc0p_aes_parents, 0x560, 16, 2, 23), 884 MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", 885 cmsys_parents, 0x560, 24, 3, 31), 886 /* CLK_CFG_17 */ 887 MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", 888 gcpu_parents, 0x570, 0, 3, 7), 889 /* CLK_AUDDIV_4 */ 890 MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel", 891 aud_apll1_parents, 0x134, 0, 1), 892 MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel", 893 aud_apll2_parents, 0x134, 1, 1), 894 MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel", 895 audull_vtx_parents, 0x134, 31, 1), 896 MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel", 897 apll1_ref_parents, 0x134, 4, 3), 898 MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel", 899 apll1_ref_parents, 0x134, 7, 3), 900 }; 901 902 static const char * const mcu_mp0_parents[] = { 903 "clk26m", 904 "armca35pll_ck", 905 "f_mp0_pll1_ck", 906 "f_mp0_pll2_ck" 907 }; 908 909 static const char * const mcu_mp2_parents[] = { 910 "clk26m", 911 "armca72pll_ck", 912 "f_big_pll1_ck", 913 "f_big_pll2_ck" 914 }; 915 916 static const char * const mcu_bus_parents[] = { 917 "clk26m", 918 "cci400_sel", 919 "f_bus_pll1_ck", 920 "f_bus_pll2_ck" 921 }; 922 923 static struct mtk_composite mcu_muxes[] = { 924 /* mp0_pll_divider_cfg */ 925 MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 926 9, 2, -1, CLK_IS_CRITICAL), 927 /* mp2_pll_divider_cfg */ 928 MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 929 9, 2, -1, CLK_IS_CRITICAL), 930 /* bus_pll_divider_cfg */ 931 MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 932 9, 2, -1, CLK_IS_CRITICAL), 933 }; 934 935 static const struct mtk_clk_divider top_adj_divs[] = { 936 DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8), 937 DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8), 938 DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8), 939 DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8), 940 DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8), 941 DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8), 942 DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8), 943 DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8), 944 }; 945 946 static const struct mtk_gate_regs top0_cg_regs = { 947 .set_ofs = 0x120, 948 .clr_ofs = 0x120, 949 .sta_ofs = 0x120, 950 }; 951 952 static const struct mtk_gate_regs top1_cg_regs = { 953 .set_ofs = 0x424, 954 .clr_ofs = 0x424, 955 .sta_ofs = 0x424, 956 }; 957 958 #define GATE_TOP0(_id, _name, _parent, _shift) { \ 959 .id = _id, \ 960 .name = _name, \ 961 .parent_name = _parent, \ 962 .regs = &top0_cg_regs, \ 963 .shift = _shift, \ 964 .ops = &mtk_clk_gate_ops_no_setclr, \ 965 } 966 967 #define GATE_TOP1(_id, _name, _parent, _shift) { \ 968 .id = _id, \ 969 .name = _name, \ 970 .parent_name = _parent, \ 971 .regs = &top1_cg_regs, \ 972 .shift = _shift, \ 973 .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 974 } 975 976 static const struct mtk_gate top_clks[] = { 977 /* TOP0 */ 978 GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0), 979 GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1), 980 GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2), 981 GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3), 982 GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4), 983 GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5), 984 GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6), 985 GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7), 986 /* TOP1 */ 987 GATE_TOP1(CLK_TOP_NFI2X_EN, "nfi2x_en", "nfi2x_sel", 0), 988 GATE_TOP1(CLK_TOP_NFIECC_EN, "nfiecc_en", "nfiecc_sel", 1), 989 GATE_TOP1(CLK_TOP_NFI1X_CK_EN, "nfi1x_ck_en", "nfi2x_sel", 2), 990 }; 991 992 static const struct mtk_gate_regs infra_cg_regs = { 993 .set_ofs = 0x40, 994 .clr_ofs = 0x44, 995 .sta_ofs = 0x48, 996 }; 997 998 #define GATE_INFRA(_id, _name, _parent, _shift) { \ 999 .id = _id, \ 1000 .name = _name, \ 1001 .parent_name = _parent, \ 1002 .regs = &infra_cg_regs, \ 1003 .shift = _shift, \ 1004 .ops = &mtk_clk_gate_ops_setclr, \ 1005 } 1006 1007 static const struct mtk_gate infra_clks[] = { 1008 GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), 1009 GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6), 1010 GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), 1011 GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), 1012 GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24), 1013 GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25), 1014 GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26), 1015 }; 1016 1017 static const struct mtk_gate_regs peri0_cg_regs = { 1018 .set_ofs = 0x8, 1019 .clr_ofs = 0x10, 1020 .sta_ofs = 0x18, 1021 }; 1022 1023 static const struct mtk_gate_regs peri1_cg_regs = { 1024 .set_ofs = 0xc, 1025 .clr_ofs = 0x14, 1026 .sta_ofs = 0x1c, 1027 }; 1028 1029 static const struct mtk_gate_regs peri2_cg_regs = { 1030 .set_ofs = 0x42c, 1031 .clr_ofs = 0x42c, 1032 .sta_ofs = 0x42c, 1033 }; 1034 1035 #define GATE_PERI0(_id, _name, _parent, _shift) { \ 1036 .id = _id, \ 1037 .name = _name, \ 1038 .parent_name = _parent, \ 1039 .regs = &peri0_cg_regs, \ 1040 .shift = _shift, \ 1041 .ops = &mtk_clk_gate_ops_setclr, \ 1042 } 1043 1044 #define GATE_PERI1(_id, _name, _parent, _shift) { \ 1045 .id = _id, \ 1046 .name = _name, \ 1047 .parent_name = _parent, \ 1048 .regs = &peri1_cg_regs, \ 1049 .shift = _shift, \ 1050 .ops = &mtk_clk_gate_ops_setclr, \ 1051 } 1052 1053 #define GATE_PERI2(_id, _name, _parent, _shift) { \ 1054 .id = _id, \ 1055 .name = _name, \ 1056 .parent_name = _parent, \ 1057 .regs = &peri2_cg_regs, \ 1058 .shift = _shift, \ 1059 .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 1060 } 1061 1062 static const struct mtk_gate peri_clks[] = { 1063 /* PERI0 */ 1064 GATE_PERI0(CLK_PERI_NFI, "per_nfi", 1065 "axi_sel", 0), 1066 GATE_PERI0(CLK_PERI_THERM, "per_therm", 1067 "axi_sel", 1), 1068 GATE_PERI0(CLK_PERI_PWM0, "per_pwm0", 1069 "pwm_sel", 2), 1070 GATE_PERI0(CLK_PERI_PWM1, "per_pwm1", 1071 "pwm_sel", 3), 1072 GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", 1073 "pwm_sel", 4), 1074 GATE_PERI0(CLK_PERI_PWM3, "per_pwm3", 1075 "pwm_sel", 5), 1076 GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", 1077 "pwm_sel", 6), 1078 GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", 1079 "pwm_sel", 7), 1080 GATE_PERI0(CLK_PERI_PWM6, "per_pwm6", 1081 "pwm_sel", 8), 1082 GATE_PERI0(CLK_PERI_PWM7, "per_pwm7", 1083 "pwm_sel", 9), 1084 GATE_PERI0(CLK_PERI_PWM, "per_pwm", 1085 "pwm_sel", 10), 1086 GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma", 1087 "axi_sel", 13), 1088 GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0", 1089 "msdc50_0_sel", 14), 1090 GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1", 1091 "msdc30_1_sel", 15), 1092 GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2", 1093 "msdc30_2_sel", 16), 1094 GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3", 1095 "msdc30_3_sel", 17), 1096 GATE_PERI0(CLK_PERI_UART0, "per_uart0", 1097 "uart_sel", 20), 1098 GATE_PERI0(CLK_PERI_UART1, "per_uart1", 1099 "uart_sel", 21), 1100 GATE_PERI0(CLK_PERI_UART2, "per_uart2", 1101 "uart_sel", 22), 1102 GATE_PERI0(CLK_PERI_UART3, "per_uart3", 1103 "uart_sel", 23), 1104 GATE_PERI0(CLK_PERI_I2C0, "per_i2c0", 1105 "axi_sel", 24), 1106 GATE_PERI0(CLK_PERI_I2C1, "per_i2c1", 1107 "axi_sel", 25), 1108 GATE_PERI0(CLK_PERI_I2C2, "per_i2c2", 1109 "axi_sel", 26), 1110 GATE_PERI0(CLK_PERI_I2C3, "per_i2c3", 1111 "axi_sel", 27), 1112 GATE_PERI0(CLK_PERI_I2C4, "per_i2c4", 1113 "axi_sel", 28), 1114 GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc", 1115 "ltepll_fs26m", 29), 1116 GATE_PERI0(CLK_PERI_SPI0, "per_spi0", 1117 "spi_sel", 30), 1118 /* PERI1 */ 1119 GATE_PERI1(CLK_PERI_SPI, "per_spi", 1120 "spinor_sel", 1), 1121 GATE_PERI1(CLK_PERI_I2C5, "per_i2c5", 1122 "axi_sel", 3), 1123 GATE_PERI1(CLK_PERI_SPI2, "per_spi2", 1124 "spi_sel", 5), 1125 GATE_PERI1(CLK_PERI_SPI3, "per_spi3", 1126 "spi_sel", 6), 1127 GATE_PERI1(CLK_PERI_SPI5, "per_spi5", 1128 "spi_sel", 8), 1129 GATE_PERI1(CLK_PERI_UART4, "per_uart4", 1130 "uart_sel", 9), 1131 GATE_PERI1(CLK_PERI_SFLASH, "per_sflash", 1132 "uart_sel", 11), 1133 GATE_PERI1(CLK_PERI_GMAC, "per_gmac", 1134 "uart_sel", 12), 1135 GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0", 1136 "uart_sel", 14), 1137 GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1", 1138 "uart_sel", 15), 1139 GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk", 1140 "uart_sel", 16), 1141 /* PERI2 */ 1142 GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en", 1143 "msdc50_0_sel", 0), 1144 GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en", 1145 "msdc30_1_sel", 1), 1146 GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en", 1147 "msdc30_2_sel", 2), 1148 GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en", 1149 "msdc30_3_sel", 3), 1150 GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h", 1151 "msdc50_0_h_sel", 4), 1152 GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h", 1153 "msdc50_3_h_sel", 5), 1154 GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q", 1155 "axi_sel", 6), 1156 GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q", 1157 "mem_sel", 7), 1158 }; 1159 1160 #define MT2712_PLL_FMAX (3000UL * MHZ) 1161 1162 #define CON0_MT2712_RST_BAR BIT(24) 1163 1164 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 1165 _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ 1166 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1167 _div_table) { \ 1168 .id = _id, \ 1169 .name = _name, \ 1170 .reg = _reg, \ 1171 .pwr_reg = _pwr_reg, \ 1172 .en_mask = _en_mask, \ 1173 .flags = _flags, \ 1174 .rst_bar_mask = CON0_MT2712_RST_BAR, \ 1175 .fmax = MT2712_PLL_FMAX, \ 1176 .pcwbits = _pcwbits, \ 1177 .pd_reg = _pd_reg, \ 1178 .pd_shift = _pd_shift, \ 1179 .tuner_reg = _tuner_reg, \ 1180 .tuner_en_reg = _tuner_en_reg, \ 1181 .tuner_en_bit = _tuner_en_bit, \ 1182 .pcw_reg = _pcw_reg, \ 1183 .pcw_shift = _pcw_shift, \ 1184 .div_table = _div_table, \ 1185 } 1186 1187 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 1188 _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ 1189 _tuner_en_bit, _pcw_reg, _pcw_shift) \ 1190 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1191 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \ 1192 _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ 1193 _pcw_shift, NULL) 1194 1195 static const struct mtk_pll_div_table armca35pll_div_table[] = { 1196 { .div = 0, .freq = MT2712_PLL_FMAX }, 1197 { .div = 1, .freq = 1202500000 }, 1198 { .div = 2, .freq = 500500000 }, 1199 { .div = 3, .freq = 315250000 }, 1200 { .div = 4, .freq = 157625000 }, 1201 { } /* sentinel */ 1202 }; 1203 1204 static const struct mtk_pll_div_table armca72pll_div_table[] = { 1205 { .div = 0, .freq = MT2712_PLL_FMAX }, 1206 { .div = 1, .freq = 994500000 }, 1207 { .div = 2, .freq = 520000000 }, 1208 { .div = 3, .freq = 315250000 }, 1209 { .div = 4, .freq = 157625000 }, 1210 { } /* sentinel */ 1211 }; 1212 1213 static const struct mtk_pll_div_table mmpll_div_table[] = { 1214 { .div = 0, .freq = MT2712_PLL_FMAX }, 1215 { .div = 1, .freq = 1001000000 }, 1216 { .div = 2, .freq = 601250000 }, 1217 { .div = 3, .freq = 250250000 }, 1218 { .div = 4, .freq = 125125000 }, 1219 { } /* sentinel */ 1220 }; 1221 1222 static const struct mtk_pll_data plls[] = { 1223 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100, 1224 HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0), 1225 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100, 1226 HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0), 1227 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100, 1228 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0), 1229 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100, 1230 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0), 1231 PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100, 1232 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0), 1233 PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100, 1234 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0), 1235 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100, 1236 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0), 1237 PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100, 1238 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0), 1239 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100, 1240 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0), 1241 PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100, 1242 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0), 1243 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100, 1244 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0), 1245 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100, 1246 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, 1247 mmpll_div_table), 1248 PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100, 1249 HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, 1250 armca35pll_div_table), 1251 PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100, 1252 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, 1253 armca72pll_div_table), 1254 PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100, 1255 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), 1256 }; 1257 1258 static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; 1259 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; 1260 1261 static const struct mtk_clk_rst_desc clk_rst_desc[] = { 1262 /* infra */ 1263 { 1264 .version = MTK_RST_SIMPLE, 1265 .rst_bank_ofs = infrasys_rst_ofs, 1266 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), 1267 }, 1268 /* peri */ 1269 { 1270 .version = MTK_RST_SIMPLE, 1271 .rst_bank_ofs = pericfg_rst_ofs, 1272 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), 1273 }, 1274 }; 1275 1276 static int clk_mt2712_apmixed_probe(struct platform_device *pdev) 1277 { 1278 struct clk_hw_onecell_data *clk_data; 1279 int r; 1280 struct device_node *node = pdev->dev.of_node; 1281 1282 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1283 1284 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1285 1286 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1287 1288 if (r != 0) 1289 pr_err("%s(): could not register clock provider: %d\n", 1290 __func__, r); 1291 1292 return r; 1293 } 1294 1295 static const struct mtk_clk_desc topck_desc = { 1296 .clks = top_clks, 1297 .num_clks = ARRAY_SIZE(top_clks), 1298 .fixed_clks = top_fixed_clks, 1299 .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 1300 .factor_clks = top_divs, 1301 .num_factor_clks = ARRAY_SIZE(top_divs), 1302 .composite_clks = top_muxes, 1303 .num_composite_clks = ARRAY_SIZE(top_muxes), 1304 .divider_clks = top_adj_divs, 1305 .num_divider_clks = ARRAY_SIZE(top_adj_divs), 1306 .clk_lock = &mt2712_clk_lock, 1307 }; 1308 1309 static const struct mtk_clk_desc mcu_desc = { 1310 .composite_clks = mcu_muxes, 1311 .num_composite_clks = ARRAY_SIZE(mcu_muxes), 1312 .clk_lock = &mt2712_clk_lock, 1313 }; 1314 1315 static const struct of_device_id of_match_clk_mt2712[] = { 1316 { 1317 .compatible = "mediatek,mt2712-apmixedsys", 1318 .data = clk_mt2712_apmixed_probe, 1319 }, { 1320 /* sentinel */ 1321 } 1322 }; 1323 1324 static int clk_mt2712_probe(struct platform_device *pdev) 1325 { 1326 int (*clk_probe)(struct platform_device *); 1327 int r; 1328 1329 clk_probe = of_device_get_match_data(&pdev->dev); 1330 if (!clk_probe) 1331 return -EINVAL; 1332 1333 r = clk_probe(pdev); 1334 if (r != 0) 1335 dev_err(&pdev->dev, 1336 "could not register clock provider: %s: %d\n", 1337 pdev->name, r); 1338 1339 return r; 1340 } 1341 1342 static const struct mtk_clk_desc infra_desc = { 1343 .clks = infra_clks, 1344 .num_clks = ARRAY_SIZE(infra_clks), 1345 .rst_desc = &clk_rst_desc[0], 1346 }; 1347 1348 static const struct mtk_clk_desc peri_desc = { 1349 .clks = peri_clks, 1350 .num_clks = ARRAY_SIZE(peri_clks), 1351 .rst_desc = &clk_rst_desc[1], 1352 }; 1353 1354 static const struct of_device_id of_match_clk_mt2712_simple[] = { 1355 { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc }, 1356 { .compatible = "mediatek,mt2712-mcucfg", .data = &mcu_desc }, 1357 { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, }, 1358 { .compatible = "mediatek,mt2712-topckgen", .data = &topck_desc }, 1359 { /* sentinel */ } 1360 }; 1361 1362 static struct platform_driver clk_mt2712_simple_drv = { 1363 .probe = mtk_clk_simple_probe, 1364 .remove = mtk_clk_simple_remove, 1365 .driver = { 1366 .name = "clk-mt2712-simple", 1367 .of_match_table = of_match_clk_mt2712_simple, 1368 }, 1369 }; 1370 1371 static struct platform_driver clk_mt2712_drv = { 1372 .probe = clk_mt2712_probe, 1373 .driver = { 1374 .name = "clk-mt2712", 1375 .of_match_table = of_match_clk_mt2712, 1376 }, 1377 }; 1378 1379 static int __init clk_mt2712_init(void) 1380 { 1381 int ret = platform_driver_register(&clk_mt2712_drv); 1382 1383 if (ret) 1384 return ret; 1385 return platform_driver_register(&clk_mt2712_simple_drv); 1386 } 1387 1388 arch_initcall(clk_mt2712_init); 1389