11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e2f744a8Sweiyi.lu@mediatek.com /* 3e2f744a8Sweiyi.lu@mediatek.com * Copyright (c) 2017 MediaTek Inc. 4e2f744a8Sweiyi.lu@mediatek.com * Author: Weiyi Lu <weiyi.lu@mediatek.com> 5e2f744a8Sweiyi.lu@mediatek.com */ 6e2f744a8Sweiyi.lu@mediatek.com 7e2f744a8Sweiyi.lu@mediatek.com #include <linux/clk-provider.h> 8e2f744a8Sweiyi.lu@mediatek.com #include <linux/platform_device.h> 9e2f744a8Sweiyi.lu@mediatek.com 10e2f744a8Sweiyi.lu@mediatek.com #include "clk-mtk.h" 11e2f744a8Sweiyi.lu@mediatek.com #include "clk-gate.h" 12e2f744a8Sweiyi.lu@mediatek.com 13e2f744a8Sweiyi.lu@mediatek.com #include <dt-bindings/clock/mt2712-clk.h> 14e2f744a8Sweiyi.lu@mediatek.com 15e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate_regs vdec0_cg_regs = { 16e2f744a8Sweiyi.lu@mediatek.com .set_ofs = 0x0, 17e2f744a8Sweiyi.lu@mediatek.com .clr_ofs = 0x4, 18e2f744a8Sweiyi.lu@mediatek.com .sta_ofs = 0x0, 19e2f744a8Sweiyi.lu@mediatek.com }; 20e2f744a8Sweiyi.lu@mediatek.com 21e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate_regs vdec1_cg_regs = { 22e2f744a8Sweiyi.lu@mediatek.com .set_ofs = 0x8, 23e2f744a8Sweiyi.lu@mediatek.com .clr_ofs = 0xc, 24e2f744a8Sweiyi.lu@mediatek.com .sta_ofs = 0x8, 25e2f744a8Sweiyi.lu@mediatek.com }; 26e2f744a8Sweiyi.lu@mediatek.com 27e2f744a8Sweiyi.lu@mediatek.com #define GATE_VDEC0(_id, _name, _parent, _shift) { \ 28e2f744a8Sweiyi.lu@mediatek.com .id = _id, \ 29e2f744a8Sweiyi.lu@mediatek.com .name = _name, \ 30e2f744a8Sweiyi.lu@mediatek.com .parent_name = _parent, \ 31e2f744a8Sweiyi.lu@mediatek.com .regs = &vdec0_cg_regs, \ 32e2f744a8Sweiyi.lu@mediatek.com .shift = _shift, \ 33e2f744a8Sweiyi.lu@mediatek.com .ops = &mtk_clk_gate_ops_setclr_inv, \ 34e2f744a8Sweiyi.lu@mediatek.com } 35e2f744a8Sweiyi.lu@mediatek.com 36e2f744a8Sweiyi.lu@mediatek.com #define GATE_VDEC1(_id, _name, _parent, _shift) { \ 37e2f744a8Sweiyi.lu@mediatek.com .id = _id, \ 38e2f744a8Sweiyi.lu@mediatek.com .name = _name, \ 39e2f744a8Sweiyi.lu@mediatek.com .parent_name = _parent, \ 40e2f744a8Sweiyi.lu@mediatek.com .regs = &vdec1_cg_regs, \ 41e2f744a8Sweiyi.lu@mediatek.com .shift = _shift, \ 42e2f744a8Sweiyi.lu@mediatek.com .ops = &mtk_clk_gate_ops_setclr_inv, \ 43e2f744a8Sweiyi.lu@mediatek.com } 44e2f744a8Sweiyi.lu@mediatek.com 45e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate vdec_clks[] = { 46e2f744a8Sweiyi.lu@mediatek.com /* VDEC0 */ 47e2f744a8Sweiyi.lu@mediatek.com GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0), 48e2f744a8Sweiyi.lu@mediatek.com /* VDEC1 */ 49e2f744a8Sweiyi.lu@mediatek.com GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0), 50e2f744a8Sweiyi.lu@mediatek.com GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1), 51e2f744a8Sweiyi.lu@mediatek.com }; 52e2f744a8Sweiyi.lu@mediatek.com 53*f3e4e735SMiles Chen static const struct mtk_clk_desc vdec_desc = { 54*f3e4e735SMiles Chen .clks = vdec_clks, 55*f3e4e735SMiles Chen .num_clks = ARRAY_SIZE(vdec_clks), 56*f3e4e735SMiles Chen }; 57e2f744a8Sweiyi.lu@mediatek.com 58e2f744a8Sweiyi.lu@mediatek.com static const struct of_device_id of_match_clk_mt2712_vdec[] = { 59*f3e4e735SMiles Chen { 60*f3e4e735SMiles Chen .compatible = "mediatek,mt2712-vdecsys", 61*f3e4e735SMiles Chen .data = &vdec_desc, 62*f3e4e735SMiles Chen }, { 63*f3e4e735SMiles Chen /* sentinel */ 64*f3e4e735SMiles Chen } 65e2f744a8Sweiyi.lu@mediatek.com }; 66e2f744a8Sweiyi.lu@mediatek.com 67e2f744a8Sweiyi.lu@mediatek.com static struct platform_driver clk_mt2712_vdec_drv = { 68*f3e4e735SMiles Chen .probe = mtk_clk_simple_probe, 69*f3e4e735SMiles Chen .remove = mtk_clk_simple_remove, 70e2f744a8Sweiyi.lu@mediatek.com .driver = { 71e2f744a8Sweiyi.lu@mediatek.com .name = "clk-mt2712-vdec", 72e2f744a8Sweiyi.lu@mediatek.com .of_match_table = of_match_clk_mt2712_vdec, 73e2f744a8Sweiyi.lu@mediatek.com }, 74e2f744a8Sweiyi.lu@mediatek.com }; 75e2f744a8Sweiyi.lu@mediatek.com 76e2f744a8Sweiyi.lu@mediatek.com builtin_platform_driver(clk_mt2712_vdec_drv); 77