1e2f744a8Sweiyi.lu@mediatek.com /* 2e2f744a8Sweiyi.lu@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3e2f744a8Sweiyi.lu@mediatek.com * Author: Weiyi Lu <weiyi.lu@mediatek.com> 4e2f744a8Sweiyi.lu@mediatek.com * 5e2f744a8Sweiyi.lu@mediatek.com * This program is free software; you can redistribute it and/or modify 6e2f744a8Sweiyi.lu@mediatek.com * it under the terms of the GNU General Public License version 2 as 7e2f744a8Sweiyi.lu@mediatek.com * published by the Free Software Foundation. 8e2f744a8Sweiyi.lu@mediatek.com * 9e2f744a8Sweiyi.lu@mediatek.com * This program is distributed in the hope that it will be useful, 10e2f744a8Sweiyi.lu@mediatek.com * but WITHOUT ANY WARRANTY; without even the implied warranty of 11e2f744a8Sweiyi.lu@mediatek.com * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12e2f744a8Sweiyi.lu@mediatek.com * GNU General Public License for more details. 13e2f744a8Sweiyi.lu@mediatek.com */ 14e2f744a8Sweiyi.lu@mediatek.com 15e2f744a8Sweiyi.lu@mediatek.com #include <linux/clk-provider.h> 16e2f744a8Sweiyi.lu@mediatek.com #include <linux/platform_device.h> 17e2f744a8Sweiyi.lu@mediatek.com 18e2f744a8Sweiyi.lu@mediatek.com #include "clk-mtk.h" 19e2f744a8Sweiyi.lu@mediatek.com #include "clk-gate.h" 20e2f744a8Sweiyi.lu@mediatek.com 21e2f744a8Sweiyi.lu@mediatek.com #include <dt-bindings/clock/mt2712-clk.h> 22e2f744a8Sweiyi.lu@mediatek.com 23e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate_regs vdec0_cg_regs = { 24e2f744a8Sweiyi.lu@mediatek.com .set_ofs = 0x0, 25e2f744a8Sweiyi.lu@mediatek.com .clr_ofs = 0x4, 26e2f744a8Sweiyi.lu@mediatek.com .sta_ofs = 0x0, 27e2f744a8Sweiyi.lu@mediatek.com }; 28e2f744a8Sweiyi.lu@mediatek.com 29e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate_regs vdec1_cg_regs = { 30e2f744a8Sweiyi.lu@mediatek.com .set_ofs = 0x8, 31e2f744a8Sweiyi.lu@mediatek.com .clr_ofs = 0xc, 32e2f744a8Sweiyi.lu@mediatek.com .sta_ofs = 0x8, 33e2f744a8Sweiyi.lu@mediatek.com }; 34e2f744a8Sweiyi.lu@mediatek.com 35e2f744a8Sweiyi.lu@mediatek.com #define GATE_VDEC0(_id, _name, _parent, _shift) { \ 36e2f744a8Sweiyi.lu@mediatek.com .id = _id, \ 37e2f744a8Sweiyi.lu@mediatek.com .name = _name, \ 38e2f744a8Sweiyi.lu@mediatek.com .parent_name = _parent, \ 39e2f744a8Sweiyi.lu@mediatek.com .regs = &vdec0_cg_regs, \ 40e2f744a8Sweiyi.lu@mediatek.com .shift = _shift, \ 41e2f744a8Sweiyi.lu@mediatek.com .ops = &mtk_clk_gate_ops_setclr_inv, \ 42e2f744a8Sweiyi.lu@mediatek.com } 43e2f744a8Sweiyi.lu@mediatek.com 44e2f744a8Sweiyi.lu@mediatek.com #define GATE_VDEC1(_id, _name, _parent, _shift) { \ 45e2f744a8Sweiyi.lu@mediatek.com .id = _id, \ 46e2f744a8Sweiyi.lu@mediatek.com .name = _name, \ 47e2f744a8Sweiyi.lu@mediatek.com .parent_name = _parent, \ 48e2f744a8Sweiyi.lu@mediatek.com .regs = &vdec1_cg_regs, \ 49e2f744a8Sweiyi.lu@mediatek.com .shift = _shift, \ 50e2f744a8Sweiyi.lu@mediatek.com .ops = &mtk_clk_gate_ops_setclr_inv, \ 51e2f744a8Sweiyi.lu@mediatek.com } 52e2f744a8Sweiyi.lu@mediatek.com 53e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate vdec_clks[] = { 54e2f744a8Sweiyi.lu@mediatek.com /* VDEC0 */ 55e2f744a8Sweiyi.lu@mediatek.com GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0), 56e2f744a8Sweiyi.lu@mediatek.com /* VDEC1 */ 57e2f744a8Sweiyi.lu@mediatek.com GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0), 58e2f744a8Sweiyi.lu@mediatek.com GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1), 59e2f744a8Sweiyi.lu@mediatek.com }; 60e2f744a8Sweiyi.lu@mediatek.com 61e2f744a8Sweiyi.lu@mediatek.com static int clk_mt2712_vdec_probe(struct platform_device *pdev) 62e2f744a8Sweiyi.lu@mediatek.com { 63e2f744a8Sweiyi.lu@mediatek.com struct clk_onecell_data *clk_data; 64e2f744a8Sweiyi.lu@mediatek.com int r; 65e2f744a8Sweiyi.lu@mediatek.com struct device_node *node = pdev->dev.of_node; 66e2f744a8Sweiyi.lu@mediatek.com 67e2f744a8Sweiyi.lu@mediatek.com clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK); 68e2f744a8Sweiyi.lu@mediatek.com 69e2f744a8Sweiyi.lu@mediatek.com mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), 70e2f744a8Sweiyi.lu@mediatek.com clk_data); 71e2f744a8Sweiyi.lu@mediatek.com 72e2f744a8Sweiyi.lu@mediatek.com r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 73e2f744a8Sweiyi.lu@mediatek.com 74e2f744a8Sweiyi.lu@mediatek.com if (r != 0) 75e2f744a8Sweiyi.lu@mediatek.com pr_err("%s(): could not register clock provider: %d\n", 76e2f744a8Sweiyi.lu@mediatek.com __func__, r); 77e2f744a8Sweiyi.lu@mediatek.com 78e2f744a8Sweiyi.lu@mediatek.com return r; 79e2f744a8Sweiyi.lu@mediatek.com } 80e2f744a8Sweiyi.lu@mediatek.com 81e2f744a8Sweiyi.lu@mediatek.com static const struct of_device_id of_match_clk_mt2712_vdec[] = { 82e2f744a8Sweiyi.lu@mediatek.com { .compatible = "mediatek,mt2712-vdecsys", }, 83e2f744a8Sweiyi.lu@mediatek.com {} 84e2f744a8Sweiyi.lu@mediatek.com }; 85e2f744a8Sweiyi.lu@mediatek.com 86e2f744a8Sweiyi.lu@mediatek.com static struct platform_driver clk_mt2712_vdec_drv = { 87e2f744a8Sweiyi.lu@mediatek.com .probe = clk_mt2712_vdec_probe, 88e2f744a8Sweiyi.lu@mediatek.com .driver = { 89e2f744a8Sweiyi.lu@mediatek.com .name = "clk-mt2712-vdec", 90e2f744a8Sweiyi.lu@mediatek.com .of_match_table = of_match_clk_mt2712_vdec, 91e2f744a8Sweiyi.lu@mediatek.com }, 92e2f744a8Sweiyi.lu@mediatek.com }; 93e2f744a8Sweiyi.lu@mediatek.com 94e2f744a8Sweiyi.lu@mediatek.com builtin_platform_driver(clk_mt2712_vdec_drv); 95