1 /* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: Weiyi Lu <weiyi.lu@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/clk-provider.h> 16 #include <linux/platform_device.h> 17 18 #include "clk-mtk.h" 19 #include "clk-gate.h" 20 21 #include <dt-bindings/clock/mt2712-clk.h> 22 23 static const struct mtk_gate_regs mm0_cg_regs = { 24 .set_ofs = 0x104, 25 .clr_ofs = 0x108, 26 .sta_ofs = 0x100, 27 }; 28 29 static const struct mtk_gate_regs mm1_cg_regs = { 30 .set_ofs = 0x114, 31 .clr_ofs = 0x118, 32 .sta_ofs = 0x110, 33 }; 34 35 static const struct mtk_gate_regs mm2_cg_regs = { 36 .set_ofs = 0x224, 37 .clr_ofs = 0x228, 38 .sta_ofs = 0x220, 39 }; 40 41 #define GATE_MM0(_id, _name, _parent, _shift) { \ 42 .id = _id, \ 43 .name = _name, \ 44 .parent_name = _parent, \ 45 .regs = &mm0_cg_regs, \ 46 .shift = _shift, \ 47 .ops = &mtk_clk_gate_ops_setclr, \ 48 } 49 50 #define GATE_MM1(_id, _name, _parent, _shift) { \ 51 .id = _id, \ 52 .name = _name, \ 53 .parent_name = _parent, \ 54 .regs = &mm1_cg_regs, \ 55 .shift = _shift, \ 56 .ops = &mtk_clk_gate_ops_setclr, \ 57 } 58 59 #define GATE_MM2(_id, _name, _parent, _shift) { \ 60 .id = _id, \ 61 .name = _name, \ 62 .parent_name = _parent, \ 63 .regs = &mm2_cg_regs, \ 64 .shift = _shift, \ 65 .ops = &mtk_clk_gate_ops_setclr, \ 66 } 67 68 static const struct mtk_gate mm_clks[] = { 69 /* MM0 */ 70 GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), 71 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), 72 GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2), 73 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3), 74 GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4), 75 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5), 76 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6), 77 GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7), 78 GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8), 79 GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9), 80 GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10), 81 GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11), 82 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12), 83 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13), 84 GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14), 85 GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15), 86 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16), 87 GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17), 88 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18), 89 GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19), 90 GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20), 91 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21), 92 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22), 93 GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23), 94 GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24), 95 GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25), 96 GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26), 97 GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27), 98 GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28), 99 GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31), 100 /* MM1 */ 101 GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0), 102 GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1), 103 GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2), 104 GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3), 105 GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4), 106 GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5), 107 GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6), 108 GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7), 109 GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8), 110 GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9), 111 GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10), 112 GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11), 113 GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16), 114 GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17), 115 GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18), 116 GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21), 117 GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22), 118 GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23), 119 GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24), 120 GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25), 121 GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26), 122 GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27), 123 GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28), 124 GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29), 125 GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30), 126 GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31), 127 /* MM2 */ 128 GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0), 129 GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1), 130 GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2), 131 GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3), 132 GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4), 133 GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5), 134 GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6), 135 }; 136 137 static int clk_mt2712_mm_probe(struct platform_device *pdev) 138 { 139 struct clk_onecell_data *clk_data; 140 int r; 141 struct device_node *node = pdev->dev.of_node; 142 143 clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); 144 145 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), 146 clk_data); 147 148 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 149 150 if (r != 0) 151 pr_err("%s(): could not register clock provider: %d\n", 152 __func__, r); 153 154 return r; 155 } 156 157 static const struct of_device_id of_match_clk_mt2712_mm[] = { 158 { .compatible = "mediatek,mt2712-mmsys", }, 159 {} 160 }; 161 162 static struct platform_driver clk_mt2712_mm_drv = { 163 .probe = clk_mt2712_mm_probe, 164 .driver = { 165 .name = "clk-mt2712-mm", 166 .of_match_table = of_match_clk_mt2712_mm, 167 }, 168 }; 169 170 builtin_platform_driver(clk_mt2712_mm_drv); 171