1e2f744a8Sweiyi.lu@mediatek.com /* 2e2f744a8Sweiyi.lu@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3e2f744a8Sweiyi.lu@mediatek.com * Author: Weiyi Lu <weiyi.lu@mediatek.com> 4e2f744a8Sweiyi.lu@mediatek.com * 5e2f744a8Sweiyi.lu@mediatek.com * This program is free software; you can redistribute it and/or modify 6e2f744a8Sweiyi.lu@mediatek.com * it under the terms of the GNU General Public License version 2 as 7e2f744a8Sweiyi.lu@mediatek.com * published by the Free Software Foundation. 8e2f744a8Sweiyi.lu@mediatek.com * 9e2f744a8Sweiyi.lu@mediatek.com * This program is distributed in the hope that it will be useful, 10e2f744a8Sweiyi.lu@mediatek.com * but WITHOUT ANY WARRANTY; without even the implied warranty of 11e2f744a8Sweiyi.lu@mediatek.com * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12e2f744a8Sweiyi.lu@mediatek.com * GNU General Public License for more details. 13e2f744a8Sweiyi.lu@mediatek.com */ 14e2f744a8Sweiyi.lu@mediatek.com 15e2f744a8Sweiyi.lu@mediatek.com #include <linux/clk-provider.h> 16e2f744a8Sweiyi.lu@mediatek.com #include <linux/platform_device.h> 17e2f744a8Sweiyi.lu@mediatek.com 18e2f744a8Sweiyi.lu@mediatek.com #include "clk-mtk.h" 19e2f744a8Sweiyi.lu@mediatek.com #include "clk-gate.h" 20e2f744a8Sweiyi.lu@mediatek.com 21e2f744a8Sweiyi.lu@mediatek.com #include <dt-bindings/clock/mt2712-clk.h> 22e2f744a8Sweiyi.lu@mediatek.com 23e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate_regs mm0_cg_regs = { 24e2f744a8Sweiyi.lu@mediatek.com .set_ofs = 0x104, 25e2f744a8Sweiyi.lu@mediatek.com .clr_ofs = 0x108, 26e2f744a8Sweiyi.lu@mediatek.com .sta_ofs = 0x100, 27e2f744a8Sweiyi.lu@mediatek.com }; 28e2f744a8Sweiyi.lu@mediatek.com 29e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate_regs mm1_cg_regs = { 30e2f744a8Sweiyi.lu@mediatek.com .set_ofs = 0x114, 31e2f744a8Sweiyi.lu@mediatek.com .clr_ofs = 0x118, 32e2f744a8Sweiyi.lu@mediatek.com .sta_ofs = 0x110, 33e2f744a8Sweiyi.lu@mediatek.com }; 34e2f744a8Sweiyi.lu@mediatek.com 35e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate_regs mm2_cg_regs = { 36e2f744a8Sweiyi.lu@mediatek.com .set_ofs = 0x224, 37e2f744a8Sweiyi.lu@mediatek.com .clr_ofs = 0x228, 38e2f744a8Sweiyi.lu@mediatek.com .sta_ofs = 0x220, 39e2f744a8Sweiyi.lu@mediatek.com }; 40e2f744a8Sweiyi.lu@mediatek.com 41e2f744a8Sweiyi.lu@mediatek.com #define GATE_MM0(_id, _name, _parent, _shift) { \ 42e2f744a8Sweiyi.lu@mediatek.com .id = _id, \ 43e2f744a8Sweiyi.lu@mediatek.com .name = _name, \ 44e2f744a8Sweiyi.lu@mediatek.com .parent_name = _parent, \ 45e2f744a8Sweiyi.lu@mediatek.com .regs = &mm0_cg_regs, \ 46e2f744a8Sweiyi.lu@mediatek.com .shift = _shift, \ 47e2f744a8Sweiyi.lu@mediatek.com .ops = &mtk_clk_gate_ops_setclr, \ 48e2f744a8Sweiyi.lu@mediatek.com } 49e2f744a8Sweiyi.lu@mediatek.com 50e2f744a8Sweiyi.lu@mediatek.com #define GATE_MM1(_id, _name, _parent, _shift) { \ 51e2f744a8Sweiyi.lu@mediatek.com .id = _id, \ 52e2f744a8Sweiyi.lu@mediatek.com .name = _name, \ 53e2f744a8Sweiyi.lu@mediatek.com .parent_name = _parent, \ 54e2f744a8Sweiyi.lu@mediatek.com .regs = &mm1_cg_regs, \ 55e2f744a8Sweiyi.lu@mediatek.com .shift = _shift, \ 56e2f744a8Sweiyi.lu@mediatek.com .ops = &mtk_clk_gate_ops_setclr, \ 57e2f744a8Sweiyi.lu@mediatek.com } 58e2f744a8Sweiyi.lu@mediatek.com 59e2f744a8Sweiyi.lu@mediatek.com #define GATE_MM2(_id, _name, _parent, _shift) { \ 60e2f744a8Sweiyi.lu@mediatek.com .id = _id, \ 61e2f744a8Sweiyi.lu@mediatek.com .name = _name, \ 62e2f744a8Sweiyi.lu@mediatek.com .parent_name = _parent, \ 63e2f744a8Sweiyi.lu@mediatek.com .regs = &mm2_cg_regs, \ 64e2f744a8Sweiyi.lu@mediatek.com .shift = _shift, \ 65e2f744a8Sweiyi.lu@mediatek.com .ops = &mtk_clk_gate_ops_setclr, \ 66e2f744a8Sweiyi.lu@mediatek.com } 67e2f744a8Sweiyi.lu@mediatek.com 68e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate mm_clks[] = { 69e2f744a8Sweiyi.lu@mediatek.com /* MM0 */ 70e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), 71e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), 72e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2), 73e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3), 74e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4), 75e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5), 76e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6), 77e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7), 78e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8), 79e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9), 80e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10), 81e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11), 82e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12), 83e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13), 84e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14), 85e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15), 86e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16), 87e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17), 88e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18), 89e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19), 90e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20), 91e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21), 92e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22), 93e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23), 94e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24), 95e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25), 96e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26), 97e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27), 98e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28), 99e2f744a8Sweiyi.lu@mediatek.com GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31), 100e2f744a8Sweiyi.lu@mediatek.com /* MM1 */ 101e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0), 102e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1), 103e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2), 104e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3), 105e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4), 106e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5), 107e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6), 108e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7), 109e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8), 110e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9), 111e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10), 112e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11), 113e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16), 114e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17), 115e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18), 116e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21), 117e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22), 118e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23), 119e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24), 120e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25), 121e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26), 122e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27), 123e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28), 124e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29), 125e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30), 126e2f744a8Sweiyi.lu@mediatek.com GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31), 127e2f744a8Sweiyi.lu@mediatek.com /* MM2 */ 128e2f744a8Sweiyi.lu@mediatek.com GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0), 129e2f744a8Sweiyi.lu@mediatek.com GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1), 130e2f744a8Sweiyi.lu@mediatek.com GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2), 131e2f744a8Sweiyi.lu@mediatek.com GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3), 132e2f744a8Sweiyi.lu@mediatek.com GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4), 133e2f744a8Sweiyi.lu@mediatek.com GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5), 134e2f744a8Sweiyi.lu@mediatek.com GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6), 135e2f744a8Sweiyi.lu@mediatek.com }; 136e2f744a8Sweiyi.lu@mediatek.com 137e2f744a8Sweiyi.lu@mediatek.com static int clk_mt2712_mm_probe(struct platform_device *pdev) 138e2f744a8Sweiyi.lu@mediatek.com { 139e2f744a8Sweiyi.lu@mediatek.com struct clk_onecell_data *clk_data; 140e2f744a8Sweiyi.lu@mediatek.com int r; 141e2f744a8Sweiyi.lu@mediatek.com struct device_node *node = pdev->dev.of_node; 142e2f744a8Sweiyi.lu@mediatek.com 143e2f744a8Sweiyi.lu@mediatek.com clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); 144e2f744a8Sweiyi.lu@mediatek.com 145e2f744a8Sweiyi.lu@mediatek.com mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), 146e2f744a8Sweiyi.lu@mediatek.com clk_data); 147e2f744a8Sweiyi.lu@mediatek.com 148e2f744a8Sweiyi.lu@mediatek.com r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 149e2f744a8Sweiyi.lu@mediatek.com 150e2f744a8Sweiyi.lu@mediatek.com if (r != 0) 151e2f744a8Sweiyi.lu@mediatek.com pr_err("%s(): could not register clock provider: %d\n", 152e2f744a8Sweiyi.lu@mediatek.com __func__, r); 153e2f744a8Sweiyi.lu@mediatek.com 154e2f744a8Sweiyi.lu@mediatek.com return r; 155e2f744a8Sweiyi.lu@mediatek.com } 156e2f744a8Sweiyi.lu@mediatek.com 157e2f744a8Sweiyi.lu@mediatek.com static const struct of_device_id of_match_clk_mt2712_mm[] = { 158e2f744a8Sweiyi.lu@mediatek.com { .compatible = "mediatek,mt2712-mmsys", }, 159e2f744a8Sweiyi.lu@mediatek.com {} 160e2f744a8Sweiyi.lu@mediatek.com }; 161e2f744a8Sweiyi.lu@mediatek.com 162e2f744a8Sweiyi.lu@mediatek.com static struct platform_driver clk_mt2712_mm_drv = { 163e2f744a8Sweiyi.lu@mediatek.com .probe = clk_mt2712_mm_probe, 164e2f744a8Sweiyi.lu@mediatek.com .driver = { 165e2f744a8Sweiyi.lu@mediatek.com .name = "clk-mt2712-mm", 166e2f744a8Sweiyi.lu@mediatek.com .of_match_table = of_match_clk_mt2712_mm, 167e2f744a8Sweiyi.lu@mediatek.com }, 168e2f744a8Sweiyi.lu@mediatek.com }; 169e2f744a8Sweiyi.lu@mediatek.com 170e2f744a8Sweiyi.lu@mediatek.com builtin_platform_driver(clk_mt2712_mm_drv); 171