1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2017 MediaTek Inc.
4  * Author: Weiyi Lu <weiyi.lu@mediatek.com>
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/platform_device.h>
9 
10 #include "clk-mtk.h"
11 #include "clk-gate.h"
12 
13 #include <dt-bindings/clock/mt2712-clk.h>
14 
15 static const struct mtk_gate_regs mfg_cg_regs = {
16 	.set_ofs = 0x4,
17 	.clr_ofs = 0x8,
18 	.sta_ofs = 0x0,
19 };
20 
21 #define GATE_MFG(_id, _name, _parent, _shift) {	\
22 		.id = _id,				\
23 		.name = _name,				\
24 		.parent_name = _parent,			\
25 		.regs = &mfg_cg_regs,			\
26 		.shift = _shift,			\
27 		.ops = &mtk_clk_gate_ops_setclr,	\
28 	}
29 
30 static const struct mtk_gate mfg_clks[] = {
31 	GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
32 };
33 
34 static int clk_mt2712_mfg_probe(struct platform_device *pdev)
35 {
36 	struct clk_hw_onecell_data *clk_data;
37 	int r;
38 	struct device_node *node = pdev->dev.of_node;
39 
40 	clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
41 
42 	mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
43 			clk_data);
44 
45 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
46 
47 	if (r != 0)
48 		pr_err("%s(): could not register clock provider: %d\n",
49 			__func__, r);
50 
51 	return r;
52 }
53 
54 static const struct of_device_id of_match_clk_mt2712_mfg[] = {
55 	{ .compatible = "mediatek,mt2712-mfgcfg", },
56 	{}
57 };
58 
59 static struct platform_driver clk_mt2712_mfg_drv = {
60 	.probe = clk_mt2712_mfg_probe,
61 	.driver = {
62 		.name = "clk-mt2712-mfg",
63 		.of_match_table = of_match_clk_mt2712_mfg,
64 	},
65 };
66 
67 builtin_platform_driver(clk_mt2712_mfg_drv);
68