11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e2f744a8Sweiyi.lu@mediatek.com /* 3e2f744a8Sweiyi.lu@mediatek.com * Copyright (c) 2017 MediaTek Inc. 4e2f744a8Sweiyi.lu@mediatek.com * Author: Weiyi Lu <weiyi.lu@mediatek.com> 5e2f744a8Sweiyi.lu@mediatek.com */ 6e2f744a8Sweiyi.lu@mediatek.com 7e2f744a8Sweiyi.lu@mediatek.com #include <linux/clk-provider.h> 8e2f744a8Sweiyi.lu@mediatek.com #include <linux/platform_device.h> 9e2f744a8Sweiyi.lu@mediatek.com 10e2f744a8Sweiyi.lu@mediatek.com #include "clk-mtk.h" 11e2f744a8Sweiyi.lu@mediatek.com #include "clk-gate.h" 12e2f744a8Sweiyi.lu@mediatek.com 13e2f744a8Sweiyi.lu@mediatek.com #include <dt-bindings/clock/mt2712-clk.h> 14e2f744a8Sweiyi.lu@mediatek.com 15e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate_regs img_cg_regs = { 16e2f744a8Sweiyi.lu@mediatek.com .set_ofs = 0x0, 17e2f744a8Sweiyi.lu@mediatek.com .clr_ofs = 0x0, 18e2f744a8Sweiyi.lu@mediatek.com .sta_ofs = 0x0, 19e2f744a8Sweiyi.lu@mediatek.com }; 20e2f744a8Sweiyi.lu@mediatek.com 21e2f744a8Sweiyi.lu@mediatek.com #define GATE_IMG(_id, _name, _parent, _shift) { \ 22e2f744a8Sweiyi.lu@mediatek.com .id = _id, \ 23e2f744a8Sweiyi.lu@mediatek.com .name = _name, \ 24e2f744a8Sweiyi.lu@mediatek.com .parent_name = _parent, \ 25e2f744a8Sweiyi.lu@mediatek.com .regs = &img_cg_regs, \ 26e2f744a8Sweiyi.lu@mediatek.com .shift = _shift, \ 27e2f744a8Sweiyi.lu@mediatek.com .ops = &mtk_clk_gate_ops_no_setclr, \ 28e2f744a8Sweiyi.lu@mediatek.com } 29e2f744a8Sweiyi.lu@mediatek.com 30e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate img_clks[] = { 31e2f744a8Sweiyi.lu@mediatek.com GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0), 32e2f744a8Sweiyi.lu@mediatek.com GATE_IMG(CLK_IMG_SENINF_SCAM_EN, "img_scam_en", "csi0", 3), 33e2f744a8Sweiyi.lu@mediatek.com GATE_IMG(CLK_IMG_SENINF_CAM_EN, "img_cam_en", "mm_sel", 8), 34e2f744a8Sweiyi.lu@mediatek.com GATE_IMG(CLK_IMG_CAM_SV_EN, "img_cam_sv_en", "mm_sel", 9), 35e2f744a8Sweiyi.lu@mediatek.com GATE_IMG(CLK_IMG_CAM_SV1_EN, "img_cam_sv1_en", "mm_sel", 10), 36e2f744a8Sweiyi.lu@mediatek.com GATE_IMG(CLK_IMG_CAM_SV2_EN, "img_cam_sv2_en", "mm_sel", 11), 37e2f744a8Sweiyi.lu@mediatek.com }; 38e2f744a8Sweiyi.lu@mediatek.com 39e2f744a8Sweiyi.lu@mediatek.com static int clk_mt2712_img_probe(struct platform_device *pdev) 40e2f744a8Sweiyi.lu@mediatek.com { 41e2f744a8Sweiyi.lu@mediatek.com struct clk_onecell_data *clk_data; 42e2f744a8Sweiyi.lu@mediatek.com int r; 43e2f744a8Sweiyi.lu@mediatek.com struct device_node *node = pdev->dev.of_node; 44e2f744a8Sweiyi.lu@mediatek.com 45e2f744a8Sweiyi.lu@mediatek.com clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK); 46e2f744a8Sweiyi.lu@mediatek.com 47e2f744a8Sweiyi.lu@mediatek.com mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), 48e2f744a8Sweiyi.lu@mediatek.com clk_data); 49e2f744a8Sweiyi.lu@mediatek.com 50e2f744a8Sweiyi.lu@mediatek.com r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 51e2f744a8Sweiyi.lu@mediatek.com 52e2f744a8Sweiyi.lu@mediatek.com if (r != 0) 53e2f744a8Sweiyi.lu@mediatek.com pr_err("%s(): could not register clock provider: %d\n", 54e2f744a8Sweiyi.lu@mediatek.com __func__, r); 55e2f744a8Sweiyi.lu@mediatek.com 56e2f744a8Sweiyi.lu@mediatek.com return r; 57e2f744a8Sweiyi.lu@mediatek.com } 58e2f744a8Sweiyi.lu@mediatek.com 59e2f744a8Sweiyi.lu@mediatek.com static const struct of_device_id of_match_clk_mt2712_img[] = { 60e2f744a8Sweiyi.lu@mediatek.com { .compatible = "mediatek,mt2712-imgsys", }, 61e2f744a8Sweiyi.lu@mediatek.com {} 62e2f744a8Sweiyi.lu@mediatek.com }; 63e2f744a8Sweiyi.lu@mediatek.com 64e2f744a8Sweiyi.lu@mediatek.com static struct platform_driver clk_mt2712_img_drv = { 65e2f744a8Sweiyi.lu@mediatek.com .probe = clk_mt2712_img_probe, 66e2f744a8Sweiyi.lu@mediatek.com .driver = { 67e2f744a8Sweiyi.lu@mediatek.com .name = "clk-mt2712-img", 68e2f744a8Sweiyi.lu@mediatek.com .of_match_table = of_match_clk_mt2712_img, 69e2f744a8Sweiyi.lu@mediatek.com }, 70e2f744a8Sweiyi.lu@mediatek.com }; 71e2f744a8Sweiyi.lu@mediatek.com 72e2f744a8Sweiyi.lu@mediatek.com builtin_platform_driver(clk_mt2712_img_drv); 73