1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2017 MediaTek Inc.
4  * Author: Weiyi Lu <weiyi.lu@mediatek.com>
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/platform_device.h>
9 
10 #include "clk-mtk.h"
11 #include "clk-gate.h"
12 
13 #include <dt-bindings/clock/mt2712-clk.h>
14 
15 static const struct mtk_gate_regs bdp_cg_regs = {
16 	.set_ofs = 0x100,
17 	.clr_ofs = 0x100,
18 	.sta_ofs = 0x100,
19 };
20 
21 #define GATE_BDP(_id, _name, _parent, _shift) {	\
22 		.id = _id,				\
23 		.name = _name,				\
24 		.parent_name = _parent,			\
25 		.regs = &bdp_cg_regs,			\
26 		.shift = _shift,			\
27 		.ops = &mtk_clk_gate_ops_no_setclr,	\
28 	}
29 
30 static const struct mtk_gate bdp_clks[] = {
31 	GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
32 	GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
33 	GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
34 	GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
35 	GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
36 	GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
37 	GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
38 	GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
39 	GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
40 	GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
41 	GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
42 	GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
43 	GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
44 	GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
45 	GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
46 	GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
47 	GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
48 	GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
49 	GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
50 	GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
51 	GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
52 	GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
53 	GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
54 	GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
55 	GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
56 	GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
57 	GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
58 	GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
59 };
60 
61 static int clk_mt2712_bdp_probe(struct platform_device *pdev)
62 {
63 	struct clk_onecell_data *clk_data;
64 	int r;
65 	struct device_node *node = pdev->dev.of_node;
66 
67 	clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);
68 
69 	mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
70 			clk_data);
71 
72 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
73 
74 	if (r != 0)
75 		pr_err("%s(): could not register clock provider: %d\n",
76 			__func__, r);
77 
78 	return r;
79 }
80 
81 static const struct of_device_id of_match_clk_mt2712_bdp[] = {
82 	{ .compatible = "mediatek,mt2712-bdpsys", },
83 	{}
84 };
85 
86 static struct platform_driver clk_mt2712_bdp_drv = {
87 	.probe = clk_mt2712_bdp_probe,
88 	.driver = {
89 		.name = "clk-mt2712-bdp",
90 		.of_match_table = of_match_clk_mt2712_bdp,
91 	},
92 };
93 
94 builtin_platform_driver(clk_mt2712_bdp_drv);
95