1e2f744a8Sweiyi.lu@mediatek.com /* 2e2f744a8Sweiyi.lu@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3e2f744a8Sweiyi.lu@mediatek.com * Author: Weiyi Lu <weiyi.lu@mediatek.com> 4e2f744a8Sweiyi.lu@mediatek.com * 5e2f744a8Sweiyi.lu@mediatek.com * This program is free software; you can redistribute it and/or modify 6e2f744a8Sweiyi.lu@mediatek.com * it under the terms of the GNU General Public License version 2 as 7e2f744a8Sweiyi.lu@mediatek.com * published by the Free Software Foundation. 8e2f744a8Sweiyi.lu@mediatek.com * 9e2f744a8Sweiyi.lu@mediatek.com * This program is distributed in the hope that it will be useful, 10e2f744a8Sweiyi.lu@mediatek.com * but WITHOUT ANY WARRANTY; without even the implied warranty of 11e2f744a8Sweiyi.lu@mediatek.com * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12e2f744a8Sweiyi.lu@mediatek.com * GNU General Public License for more details. 13e2f744a8Sweiyi.lu@mediatek.com */ 14e2f744a8Sweiyi.lu@mediatek.com 15e2f744a8Sweiyi.lu@mediatek.com #include <linux/clk-provider.h> 16e2f744a8Sweiyi.lu@mediatek.com #include <linux/platform_device.h> 17e2f744a8Sweiyi.lu@mediatek.com 18e2f744a8Sweiyi.lu@mediatek.com #include "clk-mtk.h" 19e2f744a8Sweiyi.lu@mediatek.com #include "clk-gate.h" 20e2f744a8Sweiyi.lu@mediatek.com 21e2f744a8Sweiyi.lu@mediatek.com #include <dt-bindings/clock/mt2712-clk.h> 22e2f744a8Sweiyi.lu@mediatek.com 23e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate_regs bdp_cg_regs = { 24e2f744a8Sweiyi.lu@mediatek.com .set_ofs = 0x100, 25e2f744a8Sweiyi.lu@mediatek.com .clr_ofs = 0x100, 26e2f744a8Sweiyi.lu@mediatek.com .sta_ofs = 0x100, 27e2f744a8Sweiyi.lu@mediatek.com }; 28e2f744a8Sweiyi.lu@mediatek.com 29e2f744a8Sweiyi.lu@mediatek.com #define GATE_BDP(_id, _name, _parent, _shift) { \ 30e2f744a8Sweiyi.lu@mediatek.com .id = _id, \ 31e2f744a8Sweiyi.lu@mediatek.com .name = _name, \ 32e2f744a8Sweiyi.lu@mediatek.com .parent_name = _parent, \ 33e2f744a8Sweiyi.lu@mediatek.com .regs = &bdp_cg_regs, \ 34e2f744a8Sweiyi.lu@mediatek.com .shift = _shift, \ 35e2f744a8Sweiyi.lu@mediatek.com .ops = &mtk_clk_gate_ops_no_setclr, \ 36e2f744a8Sweiyi.lu@mediatek.com } 37e2f744a8Sweiyi.lu@mediatek.com 38e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate bdp_clks[] = { 39e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0), 40e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1), 41e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2), 42e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3), 43e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4), 44e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5), 45e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9), 46e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10), 47e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11), 48e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12), 49e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13), 50e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14), 51e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15), 52e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16), 53e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17), 54e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18), 55e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19), 56e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20), 57e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21), 58e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22), 59e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23), 60e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24), 61e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25), 62e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26), 63e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27), 64e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28), 65e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29), 66e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30), 67e2f744a8Sweiyi.lu@mediatek.com }; 68e2f744a8Sweiyi.lu@mediatek.com 69e2f744a8Sweiyi.lu@mediatek.com static int clk_mt2712_bdp_probe(struct platform_device *pdev) 70e2f744a8Sweiyi.lu@mediatek.com { 71e2f744a8Sweiyi.lu@mediatek.com struct clk_onecell_data *clk_data; 72e2f744a8Sweiyi.lu@mediatek.com int r; 73e2f744a8Sweiyi.lu@mediatek.com struct device_node *node = pdev->dev.of_node; 74e2f744a8Sweiyi.lu@mediatek.com 75e2f744a8Sweiyi.lu@mediatek.com clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK); 76e2f744a8Sweiyi.lu@mediatek.com 77e2f744a8Sweiyi.lu@mediatek.com mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks), 78e2f744a8Sweiyi.lu@mediatek.com clk_data); 79e2f744a8Sweiyi.lu@mediatek.com 80e2f744a8Sweiyi.lu@mediatek.com r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 81e2f744a8Sweiyi.lu@mediatek.com 82e2f744a8Sweiyi.lu@mediatek.com if (r != 0) 83e2f744a8Sweiyi.lu@mediatek.com pr_err("%s(): could not register clock provider: %d\n", 84e2f744a8Sweiyi.lu@mediatek.com __func__, r); 85e2f744a8Sweiyi.lu@mediatek.com 86e2f744a8Sweiyi.lu@mediatek.com return r; 87e2f744a8Sweiyi.lu@mediatek.com } 88e2f744a8Sweiyi.lu@mediatek.com 89e2f744a8Sweiyi.lu@mediatek.com static const struct of_device_id of_match_clk_mt2712_bdp[] = { 90e2f744a8Sweiyi.lu@mediatek.com { .compatible = "mediatek,mt2712-bdpsys", }, 91e2f744a8Sweiyi.lu@mediatek.com {} 92e2f744a8Sweiyi.lu@mediatek.com }; 93e2f744a8Sweiyi.lu@mediatek.com 94e2f744a8Sweiyi.lu@mediatek.com static struct platform_driver clk_mt2712_bdp_drv = { 95e2f744a8Sweiyi.lu@mediatek.com .probe = clk_mt2712_bdp_probe, 96e2f744a8Sweiyi.lu@mediatek.com .driver = { 97e2f744a8Sweiyi.lu@mediatek.com .name = "clk-mt2712-bdp", 98e2f744a8Sweiyi.lu@mediatek.com .of_match_table = of_match_clk_mt2712_bdp, 99e2f744a8Sweiyi.lu@mediatek.com }, 100e2f744a8Sweiyi.lu@mediatek.com }; 101e2f744a8Sweiyi.lu@mediatek.com 102e2f744a8Sweiyi.lu@mediatek.com builtin_platform_driver(clk_mt2712_bdp_drv); 103