1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Shunli Wang <shunli.wang@mediatek.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/of_device.h> 11 #include <linux/platform_device.h> 12 13 #include "clk-cpumux.h" 14 #include "clk-gate.h" 15 #include "clk-mtk.h" 16 #include "clk-pll.h" 17 18 #include <dt-bindings/clock/mt2701-clk.h> 19 20 /* 21 * For some clocks, we don't care what their actual rates are. And these 22 * clocks may change their rate on different products or different scenarios. 23 * So we model these clocks' rate as 0, to denote it's not an actual rate. 24 */ 25 #define DUMMY_RATE 0 26 27 static DEFINE_SPINLOCK(mt2701_clk_lock); 28 29 static const struct mtk_fixed_clk top_fixed_clks[] = { 30 FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m", 31 108 * MHZ), 32 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m", 33 400 * MHZ), 34 FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m", 35 295750000), 36 FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m", 37 340 * MHZ), 38 FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m", 39 340 * MHZ), 40 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m", 41 340 * MHZ), 42 FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m", 43 27 * MHZ), 44 FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m", 45 416 * MHZ), 46 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m", 47 143 * MHZ), 48 FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m", 49 27 * MHZ), 50 FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m", 51 DUMMY_RATE), 52 FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m", 53 DUMMY_RATE), 54 FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m", 55 DUMMY_RATE), 56 }; 57 58 static const struct mtk_fixed_factor top_fixed_divs[] = { 59 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1), 60 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 61 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3), 62 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 63 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), 64 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2), 65 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4), 66 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8), 67 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16), 68 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2), 69 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4), 70 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8), 71 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2), 72 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4), 73 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2), 74 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4), 75 76 FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1), 77 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 78 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 79 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 80 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 81 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26), 82 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52), 83 FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108), 84 FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26), 85 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2), 86 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4), 87 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8), 88 FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1), 89 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2), 90 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4), 91 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8), 92 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16), 93 FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32), 94 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2), 95 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4), 96 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8), 97 98 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 99 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 100 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 101 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8), 102 103 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), 104 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 105 106 FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2), 107 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4), 108 FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1), 109 110 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), 111 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2), 112 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 113 114 FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1), 115 FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1), 116 FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2), 117 118 FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1), 119 FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2), 120 FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4), 121 122 FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1), 123 FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2), 124 FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3), 125 126 FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1), 127 128 FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1), 129 FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4), 130 FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8), 131 FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16), 132 FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24), 133 134 FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3), 135 FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3), 136 FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3), 137 FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1), 138 FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1), 139 FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8), 140 FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793), 141 FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1), 142 FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4), 143 }; 144 145 static const char * const axi_parents[] = { 146 "clk26m", 147 "syspll1_d2", 148 "syspll_d5", 149 "syspll1_d4", 150 "univpll_d5", 151 "univpll2_d2", 152 "mmpll_d2", 153 "dmpll_d2" 154 }; 155 156 static const char * const mem_parents[] = { 157 "clk26m", 158 "dmpll_ck" 159 }; 160 161 static const char * const ddrphycfg_parents[] = { 162 "clk26m", 163 "syspll1_d8" 164 }; 165 166 static const char * const mm_parents[] = { 167 "clk26m", 168 "vencpll_ck", 169 "syspll1_d2", 170 "syspll1_d4", 171 "univpll_d5", 172 "univpll1_d2", 173 "univpll2_d2", 174 "dmpll_ck" 175 }; 176 177 static const char * const pwm_parents[] = { 178 "clk26m", 179 "univpll2_d4", 180 "univpll3_d2", 181 "univpll1_d4", 182 }; 183 184 static const char * const vdec_parents[] = { 185 "clk26m", 186 "vdecpll_ck", 187 "syspll_d5", 188 "syspll1_d4", 189 "univpll_d5", 190 "univpll2_d2", 191 "vencpll_ck", 192 "msdcpll_d2", 193 "mmpll_d2" 194 }; 195 196 static const char * const mfg_parents[] = { 197 "clk26m", 198 "mmpll_ck", 199 "dmpll_x2_ck", 200 "msdcpll_ck", 201 "clk26m", 202 "syspll_d3", 203 "univpll_d3", 204 "univpll1_d2" 205 }; 206 207 static const char * const camtg_parents[] = { 208 "clk26m", 209 "univpll_d26", 210 "univpll2_d2", 211 "syspll3_d2", 212 "syspll3_d4", 213 "msdcpll_d2", 214 "mmpll_d2" 215 }; 216 217 static const char * const uart_parents[] = { 218 "clk26m", 219 "univpll2_d8" 220 }; 221 222 static const char * const spi_parents[] = { 223 "clk26m", 224 "syspll3_d2", 225 "syspll4_d2", 226 "univpll2_d4", 227 "univpll1_d8" 228 }; 229 230 static const char * const usb20_parents[] = { 231 "clk26m", 232 "univpll1_d8", 233 "univpll3_d4" 234 }; 235 236 static const char * const msdc30_parents[] = { 237 "clk26m", 238 "msdcpll_d2", 239 "syspll2_d2", 240 "syspll1_d4", 241 "univpll1_d4", 242 "univpll2_d4" 243 }; 244 245 static const char * const aud_intbus_parents[] = { 246 "clk26m", 247 "syspll1_d4", 248 "syspll3_d2", 249 "syspll4_d2", 250 "univpll3_d2", 251 "univpll2_d4" 252 }; 253 254 static const char * const pmicspi_parents[] = { 255 "clk26m", 256 "syspll1_d8", 257 "syspll2_d4", 258 "syspll4_d2", 259 "syspll3_d4", 260 "syspll2_d8", 261 "syspll1_d16", 262 "univpll3_d4", 263 "univpll_d26", 264 "dmpll_d2", 265 "dmpll_d4" 266 }; 267 268 static const char * const scp_parents[] = { 269 "clk26m", 270 "syspll1_d8", 271 "dmpll_d2", 272 "dmpll_d4" 273 }; 274 275 static const char * const dpi0_parents[] = { 276 "clk26m", 277 "mipipll", 278 "mipipll_d2", 279 "mipipll_d4", 280 "clk26m", 281 "tvdpll_ck", 282 "tvdpll_d2", 283 "tvdpll_d4" 284 }; 285 286 static const char * const dpi1_parents[] = { 287 "clk26m", 288 "tvdpll_ck", 289 "tvdpll_d2", 290 "tvdpll_d4" 291 }; 292 293 static const char * const tve_parents[] = { 294 "clk26m", 295 "mipipll", 296 "mipipll_d2", 297 "mipipll_d4", 298 "clk26m", 299 "tvdpll_ck", 300 "tvdpll_d2", 301 "tvdpll_d4" 302 }; 303 304 static const char * const hdmi_parents[] = { 305 "clk26m", 306 "hdmipll_ck", 307 "hdmipll_d2", 308 "hdmipll_d3" 309 }; 310 311 static const char * const apll_parents[] = { 312 "clk26m", 313 "audpll", 314 "audpll_d4", 315 "audpll_d8", 316 "audpll_d16", 317 "audpll_d24", 318 "clk26m", 319 "clk26m" 320 }; 321 322 static const char * const rtc_parents[] = { 323 "32k_internal", 324 "32k_external", 325 "clk26m", 326 "univpll3_d8" 327 }; 328 329 static const char * const nfi2x_parents[] = { 330 "clk26m", 331 "syspll2_d2", 332 "syspll_d7", 333 "univpll3_d2", 334 "syspll2_d4", 335 "univpll3_d4", 336 "syspll4_d4", 337 "clk26m" 338 }; 339 340 static const char * const emmc_hclk_parents[] = { 341 "clk26m", 342 "syspll1_d2", 343 "syspll1_d4", 344 "syspll2_d2" 345 }; 346 347 static const char * const flash_parents[] = { 348 "clk26m_d8", 349 "clk26m", 350 "syspll2_d8", 351 "syspll3_d4", 352 "univpll3_d4", 353 "syspll4_d2", 354 "syspll2_d4", 355 "univpll2_d4" 356 }; 357 358 static const char * const di_parents[] = { 359 "clk26m", 360 "tvd2pll_ck", 361 "tvd2pll_d2", 362 "clk26m" 363 }; 364 365 static const char * const nr_osd_parents[] = { 366 "clk26m", 367 "vencpll_ck", 368 "syspll1_d2", 369 "syspll1_d4", 370 "univpll_d5", 371 "univpll1_d2", 372 "univpll2_d2", 373 "dmpll_ck" 374 }; 375 376 static const char * const hdmirx_bist_parents[] = { 377 "clk26m", 378 "syspll_d3", 379 "clk26m", 380 "syspll1_d16", 381 "syspll4_d2", 382 "syspll1_d4", 383 "vencpll_ck", 384 "clk26m" 385 }; 386 387 static const char * const intdir_parents[] = { 388 "clk26m", 389 "mmpll_ck", 390 "syspll_d2", 391 "univpll_d2" 392 }; 393 394 static const char * const asm_parents[] = { 395 "clk26m", 396 "univpll2_d4", 397 "univpll2_d2", 398 "syspll_d5" 399 }; 400 401 static const char * const ms_card_parents[] = { 402 "clk26m", 403 "univpll3_d8", 404 "syspll4_d4" 405 }; 406 407 static const char * const ethif_parents[] = { 408 "clk26m", 409 "syspll1_d2", 410 "syspll_d5", 411 "syspll1_d4", 412 "univpll_d5", 413 "univpll1_d2", 414 "dmpll_ck", 415 "dmpll_d2" 416 }; 417 418 static const char * const hdmirx_parents[] = { 419 "clk26m", 420 "univpll_d52" 421 }; 422 423 static const char * const cmsys_parents[] = { 424 "clk26m", 425 "syspll1_d2", 426 "univpll1_d2", 427 "univpll_d5", 428 "syspll_d5", 429 "syspll2_d2", 430 "syspll1_d4", 431 "syspll3_d2", 432 "syspll2_d4", 433 "syspll1_d8", 434 "clk26m", 435 "clk26m", 436 "clk26m", 437 "clk26m", 438 "clk26m" 439 }; 440 441 static const char * const clk_8bdac_parents[] = { 442 "32k_internal", 443 "8bdac_ck", 444 "clk26m", 445 "clk26m" 446 }; 447 448 static const char * const aud2dvd_parents[] = { 449 "a1sys_hp_ck", 450 "a2sys_hp_ck" 451 }; 452 453 static const char * const padmclk_parents[] = { 454 "clk26m", 455 "univpll_d26", 456 "univpll_d52", 457 "univpll_d108", 458 "univpll2_d8", 459 "univpll2_d16", 460 "univpll2_d32" 461 }; 462 463 static const char * const aud_mux_parents[] = { 464 "clk26m", 465 "aud1pll_98m_ck", 466 "aud2pll_90m_ck", 467 "hadds2pll_98m", 468 "audio_ext1_ck", 469 "audio_ext2_ck" 470 }; 471 472 static const char * const aud_src_parents[] = { 473 "aud_mux1_sel", 474 "aud_mux2_sel" 475 }; 476 477 static const char * const cpu_parents[] = { 478 "clk26m", 479 "armpll", 480 "mainpll", 481 "mmpll" 482 }; 483 484 static const struct mtk_composite cpu_muxes[] __initconst = { 485 MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2), 486 }; 487 488 static const struct mtk_composite top_muxes[] = { 489 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 490 0x0040, 0, 3, 7, CLK_IS_CRITICAL), 491 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 492 0x0040, 8, 1, 15, CLK_IS_CRITICAL), 493 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", 494 ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL), 495 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 496 0x0040, 24, 3, 31), 497 498 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 499 0x0050, 0, 2, 7), 500 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 501 0x0050, 8, 4, 15), 502 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 503 0x0050, 16, 3, 23), 504 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 505 0x0050, 24, 3, 31), 506 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 507 0x0060, 0, 1, 7), 508 509 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents, 510 0x0060, 8, 3, 15), 511 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 512 0x0060, 16, 2, 23), 513 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 514 0x0060, 24, 3, 31), 515 516 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 517 0x0070, 0, 3, 7), 518 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 519 0x0070, 8, 3, 15), 520 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents, 521 0x0070, 16, 1, 23), 522 MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 523 0x0070, 24, 3, 31), 524 525 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 526 0x0080, 0, 4, 7), 527 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 528 0x0080, 8, 2, 15), 529 MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 530 0x0080, 16, 3, 23), 531 MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 532 0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST), 533 534 MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, 535 0x0090, 0, 3, 7), 536 MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 537 0x0090, 8, 2, 15), 538 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 539 0x0090, 16, 3, 23), 540 541 MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 542 0x00A0, 0, 2, 7, CLK_IS_CRITICAL), 543 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 544 0x00A0, 8, 3, 15), 545 MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents, 546 0x00A0, 24, 2, 31), 547 548 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents, 549 0x00B0, 0, 3, 7), 550 MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents, 551 0x00B0, 8, 2, 15), 552 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents, 553 0x00B0, 16, 3, 23), 554 MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents, 555 0x00B0, 24, 3, 31), 556 557 MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel", 558 hdmirx_bist_parents, 0x00C0, 0, 3, 7), 559 MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents, 560 0x00C0, 8, 2, 15), 561 MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents, 562 0x00C0, 16, 2, 23), 563 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents, 564 0x00C0, 24, 3, 31), 565 566 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents, 567 0x00D0, 0, 2, 7), 568 MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents, 569 0x00D0, 16, 2, 23), 570 MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents, 571 0x00D0, 24, 3, 31), 572 573 MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents, 574 0x00E0, 0, 1, 7), 575 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 576 0x00E0, 8, 3, 15), 577 MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents, 578 0x00E0, 16, 4, 23), 579 580 MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents, 581 0x00E0, 24, 3, 31), 582 MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents, 583 0x00F0, 0, 3, 7), 584 MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents, 585 0x00F0, 8, 2, 15), 586 MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents, 587 0x00F0, 16, 1, 23), 588 589 MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents, 590 0x0100, 0, 3), 591 592 MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents, 593 0x012c, 0, 3), 594 MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents, 595 0x012c, 3, 3), 596 MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents, 597 0x012c, 6, 3), 598 MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents, 599 0x012c, 15, 1, 23), 600 MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents, 601 0x012c, 16, 1, 24), 602 MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents, 603 0x012c, 17, 1, 25), 604 MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents, 605 0x012c, 18, 1, 26), 606 MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents, 607 0x012c, 19, 1, 27), 608 MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents, 609 0x012c, 20, 1, 28), 610 }; 611 612 static const struct mtk_clk_divider top_adj_divs[] = { 613 DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1", 614 0x0120, 0, 8), 615 DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2", 616 0x0120, 8, 8), 617 DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel", 618 0x0120, 16, 8), 619 DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel", 620 0x0120, 24, 8), 621 DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel", 622 0x0124, 0, 8), 623 DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel", 624 0x0124, 8, 8), 625 DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel", 626 0x0124, 16, 8), 627 DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel", 628 0x0124, 24, 8), 629 DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel", 630 0x0128, 0, 8), 631 DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel", 632 0x0128, 8, 8), 633 }; 634 635 static const struct mtk_gate_regs top_aud_cg_regs = { 636 .sta_ofs = 0x012C, 637 }; 638 639 #define GATE_TOP_AUD(_id, _name, _parent, _shift) \ 640 GATE_MTK(_id, _name, _parent, &top_aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 641 642 static const struct mtk_gate top_clks[] = { 643 GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div", 644 21), 645 GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div", 646 22), 647 GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div", 648 23), 649 GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div", 650 24), 651 GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div", 652 25), 653 GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div", 654 26), 655 GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div", 656 27), 657 GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 658 28), 659 }; 660 661 static int mtk_topckgen_init(struct platform_device *pdev) 662 { 663 struct clk_hw_onecell_data *clk_data; 664 void __iomem *base; 665 struct device_node *node = pdev->dev.of_node; 666 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 667 668 base = devm_ioremap_resource(&pdev->dev, res); 669 if (IS_ERR(base)) 670 return PTR_ERR(base); 671 672 clk_data = mtk_alloc_clk_data(CLK_TOP_NR); 673 674 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 675 clk_data); 676 677 mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), 678 clk_data); 679 680 mtk_clk_register_composites(&pdev->dev, top_muxes, 681 ARRAY_SIZE(top_muxes), base, 682 &mt2701_clk_lock, clk_data); 683 684 mtk_clk_register_dividers(&pdev->dev, top_adj_divs, ARRAY_SIZE(top_adj_divs), 685 base, &mt2701_clk_lock, clk_data); 686 687 mtk_clk_register_gates(&pdev->dev, node, top_clks, 688 ARRAY_SIZE(top_clks), clk_data); 689 690 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 691 } 692 693 static const struct mtk_gate_regs infra_cg_regs = { 694 .set_ofs = 0x0040, 695 .clr_ofs = 0x0044, 696 .sta_ofs = 0x0048, 697 }; 698 699 #define GATE_ICG(_id, _name, _parent, _shift) \ 700 GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 701 702 static const struct mtk_gate infra_clks[] = { 703 GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0), 704 GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1), 705 GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2), 706 GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4), 707 GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5), 708 GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6), 709 GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7), 710 GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), 711 GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12), 712 GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13), 713 GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14), 714 GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15), 715 GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16), 716 GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18), 717 GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19), 718 GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), 719 GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23), 720 GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24), 721 }; 722 723 static const struct mtk_fixed_factor infra_fixed_divs[] = { 724 FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), 725 }; 726 727 static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; 728 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; 729 730 static const struct mtk_clk_rst_desc clk_rst_desc[] = { 731 /* infrasys */ 732 { 733 .version = MTK_RST_SIMPLE, 734 .rst_bank_ofs = infrasys_rst_ofs, 735 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), 736 }, 737 /* pericfg */ 738 { 739 .version = MTK_RST_SIMPLE, 740 .rst_bank_ofs = pericfg_rst_ofs, 741 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), 742 }, 743 }; 744 745 static struct clk_hw_onecell_data *infra_clk_data; 746 747 static void __init mtk_infrasys_init_early(struct device_node *node) 748 { 749 int r, i; 750 751 if (!infra_clk_data) { 752 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); 753 754 for (i = 0; i < CLK_INFRA_NR; i++) 755 infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 756 } 757 758 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), 759 infra_clk_data); 760 761 mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes), 762 infra_clk_data); 763 764 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 765 infra_clk_data); 766 if (r) 767 pr_err("%s(): could not register clock provider: %d\n", 768 __func__, r); 769 } 770 CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg", 771 mtk_infrasys_init_early); 772 773 static int mtk_infrasys_init(struct platform_device *pdev) 774 { 775 int r, i; 776 struct device_node *node = pdev->dev.of_node; 777 778 if (!infra_clk_data) { 779 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); 780 } else { 781 for (i = 0; i < CLK_INFRA_NR; i++) { 782 if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER)) 783 infra_clk_data->hws[i] = ERR_PTR(-ENOENT); 784 } 785 } 786 787 mtk_clk_register_gates(&pdev->dev, node, infra_clks, 788 ARRAY_SIZE(infra_clks), infra_clk_data); 789 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), 790 infra_clk_data); 791 792 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 793 infra_clk_data); 794 if (r) 795 return r; 796 797 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); 798 799 return 0; 800 } 801 802 static const struct mtk_gate_regs peri0_cg_regs = { 803 .set_ofs = 0x0008, 804 .clr_ofs = 0x0010, 805 .sta_ofs = 0x0018, 806 }; 807 808 static const struct mtk_gate_regs peri1_cg_regs = { 809 .set_ofs = 0x000c, 810 .clr_ofs = 0x0014, 811 .sta_ofs = 0x001c, 812 }; 813 814 #define GATE_PERI0(_id, _name, _parent, _shift) \ 815 GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 816 817 #define GATE_PERI1(_id, _name, _parent, _shift) \ 818 GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 819 820 static const struct mtk_gate peri_clks[] = { 821 GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31), 822 GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30), 823 GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29), 824 GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28), 825 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27), 826 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26), 827 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25), 828 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24), 829 GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23), 830 GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22), 831 GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21), 832 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20), 833 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19), 834 GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18), 835 GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17), 836 GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16), 837 GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15), 838 GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14), 839 GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13), 840 GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12), 841 GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11), 842 GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10), 843 GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9), 844 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8), 845 GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7), 846 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6), 847 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5), 848 GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4), 849 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3), 850 GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2), 851 GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1), 852 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0), 853 854 GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11), 855 GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10), 856 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9), 857 GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8), 858 GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7), 859 GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6), 860 GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5), 861 GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4), 862 GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3), 863 GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2), 864 GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1), 865 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0), 866 }; 867 868 static const char * const uart_ck_sel_parents[] = { 869 "clk26m", 870 "uart_sel", 871 }; 872 873 static const struct mtk_composite peri_muxs[] = { 874 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 875 0x40c, 0, 1), 876 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 877 0x40c, 1, 1), 878 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 879 0x40c, 2, 1), 880 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 881 0x40c, 3, 1), 882 }; 883 884 static int mtk_pericfg_init(struct platform_device *pdev) 885 { 886 struct clk_hw_onecell_data *clk_data; 887 void __iomem *base; 888 int r; 889 struct device_node *node = pdev->dev.of_node; 890 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 891 892 base = devm_ioremap_resource(&pdev->dev, res); 893 if (IS_ERR(base)) 894 return PTR_ERR(base); 895 896 clk_data = mtk_alloc_clk_data(CLK_PERI_NR); 897 898 mtk_clk_register_gates(&pdev->dev, node, peri_clks, 899 ARRAY_SIZE(peri_clks), clk_data); 900 901 mtk_clk_register_composites(&pdev->dev, peri_muxs, 902 ARRAY_SIZE(peri_muxs), base, 903 &mt2701_clk_lock, clk_data); 904 905 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 906 if (r) 907 return r; 908 909 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); 910 911 return 0; 912 } 913 914 #define MT8590_PLL_FMAX (2000 * MHZ) 915 #define CON0_MT8590_RST_BAR BIT(27) 916 917 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 918 _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ 919 .id = _id, \ 920 .name = _name, \ 921 .reg = _reg, \ 922 .pwr_reg = _pwr_reg, \ 923 .en_mask = _en_mask, \ 924 .flags = _flags, \ 925 .rst_bar_mask = CON0_MT8590_RST_BAR, \ 926 .fmax = MT8590_PLL_FMAX, \ 927 .pcwbits = _pcwbits, \ 928 .pd_reg = _pd_reg, \ 929 .pd_shift = _pd_shift, \ 930 .tuner_reg = _tuner_reg, \ 931 .pcw_reg = _pcw_reg, \ 932 .pcw_shift = _pcw_shift, \ 933 } 934 935 static const struct mtk_pll_data apmixed_plls[] = { 936 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000, 937 PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0), 938 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000, 939 HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0), 940 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000, 941 HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14), 942 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0, 0, 943 21, 0x230, 4, 0x0, 0x234, 0), 944 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0, 945 21, 0x240, 4, 0x0, 0x244, 0), 946 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0, 947 21, 0x250, 4, 0x0, 0x254, 0), 948 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0, 949 31, 0x270, 4, 0x0, 0x274, 0), 950 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0, 951 31, 0x280, 4, 0x0, 0x284, 0), 952 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0, 953 31, 0x290, 4, 0x0, 0x294, 0), 954 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0, 955 31, 0x2a0, 4, 0x0, 0x2a4, 0), 956 PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0, 957 31, 0x2b0, 4, 0x0, 0x2b4, 0), 958 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0, 959 31, 0x2c0, 4, 0x0, 0x2c4, 0), 960 PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0, 961 21, 0x2d0, 4, 0x0, 0x2d4, 0), 962 }; 963 964 static const struct mtk_fixed_factor apmixed_fixed_divs[] = { 965 FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1), 966 }; 967 968 static int mtk_apmixedsys_init(struct platform_device *pdev) 969 { 970 struct clk_hw_onecell_data *clk_data; 971 struct device_node *node = pdev->dev.of_node; 972 973 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR); 974 if (!clk_data) 975 return -ENOMEM; 976 977 mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls), 978 clk_data); 979 mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs), 980 clk_data); 981 982 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 983 } 984 985 static const struct of_device_id of_match_clk_mt2701[] = { 986 { 987 .compatible = "mediatek,mt2701-topckgen", 988 .data = mtk_topckgen_init, 989 }, { 990 .compatible = "mediatek,mt2701-infracfg", 991 .data = mtk_infrasys_init, 992 }, { 993 .compatible = "mediatek,mt2701-pericfg", 994 .data = mtk_pericfg_init, 995 }, { 996 .compatible = "mediatek,mt2701-apmixedsys", 997 .data = mtk_apmixedsys_init, 998 }, { 999 /* sentinel */ 1000 } 1001 }; 1002 MODULE_DEVICE_TABLE(of, of_match_clk_mt2701); 1003 1004 static int clk_mt2701_probe(struct platform_device *pdev) 1005 { 1006 int (*clk_init)(struct platform_device *); 1007 int r; 1008 1009 clk_init = of_device_get_match_data(&pdev->dev); 1010 if (!clk_init) 1011 return -EINVAL; 1012 1013 r = clk_init(pdev); 1014 if (r) 1015 dev_err(&pdev->dev, 1016 "could not register clock provider: %s: %d\n", 1017 pdev->name, r); 1018 1019 return r; 1020 } 1021 1022 static struct platform_driver clk_mt2701_drv = { 1023 .probe = clk_mt2701_probe, 1024 .driver = { 1025 .name = "clk-mt2701", 1026 .of_match_table = of_match_clk_mt2701, 1027 }, 1028 }; 1029 1030 static int __init clk_mt2701_init(void) 1031 { 1032 return platform_driver_register(&clk_mt2701_drv); 1033 } 1034 1035 arch_initcall(clk_mt2701_init); 1036 MODULE_LICENSE("GPL"); 1037