1e9862118SShunli Wang /*
2e9862118SShunli Wang  * Copyright (c) 2014 MediaTek Inc.
3e9862118SShunli Wang  * Author: Shunli Wang <shunli.wang@mediatek.com>
4e9862118SShunli Wang  *
5e9862118SShunli Wang  * This program is free software; you can redistribute it and/or modify
6e9862118SShunli Wang  * it under the terms of the GNU General Public License version 2 as
7e9862118SShunli Wang  * published by the Free Software Foundation.
8e9862118SShunli Wang  *
9e9862118SShunli Wang  * This program is distributed in the hope that it will be useful,
10e9862118SShunli Wang  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11e9862118SShunli Wang  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12e9862118SShunli Wang  * GNU General Public License for more details.
13e9862118SShunli Wang  */
14e9862118SShunli Wang 
15e9862118SShunli Wang #include <linux/clk-provider.h>
16e9862118SShunli Wang #include <linux/platform_device.h>
17e9862118SShunli Wang 
18e9862118SShunli Wang #include "clk-mtk.h"
19e9862118SShunli Wang #include "clk-gate.h"
20e9862118SShunli Wang 
21e9862118SShunli Wang #include <dt-bindings/clock/mt2701-clk.h>
22e9862118SShunli Wang 
23e9862118SShunli Wang static const struct mtk_gate_regs vdec0_cg_regs = {
24e9862118SShunli Wang 	.set_ofs = 0x0000,
25e9862118SShunli Wang 	.clr_ofs = 0x0004,
26e9862118SShunli Wang 	.sta_ofs = 0x0000,
27e9862118SShunli Wang };
28e9862118SShunli Wang 
29e9862118SShunli Wang static const struct mtk_gate_regs vdec1_cg_regs = {
30e9862118SShunli Wang 	.set_ofs = 0x0008,
31e9862118SShunli Wang 	.clr_ofs = 0x000c,
32e9862118SShunli Wang 	.sta_ofs = 0x0008,
33e9862118SShunli Wang };
34e9862118SShunli Wang 
35e9862118SShunli Wang #define GATE_VDEC0(_id, _name, _parent, _shift) {	\
36e9862118SShunli Wang 		.id = _id,				\
37e9862118SShunli Wang 		.name = _name,				\
38e9862118SShunli Wang 		.parent_name = _parent,			\
39e9862118SShunli Wang 		.regs = &vdec0_cg_regs,			\
40e9862118SShunli Wang 		.shift = _shift,			\
41e9862118SShunli Wang 		.ops = &mtk_clk_gate_ops_setclr_inv,	\
42e9862118SShunli Wang 	}
43e9862118SShunli Wang 
44e9862118SShunli Wang #define GATE_VDEC1(_id, _name, _parent, _shift) {	\
45e9862118SShunli Wang 		.id = _id,				\
46e9862118SShunli Wang 		.name = _name,				\
47e9862118SShunli Wang 		.parent_name = _parent,			\
48e9862118SShunli Wang 		.regs = &vdec1_cg_regs,			\
49e9862118SShunli Wang 		.shift = _shift,			\
50e9862118SShunli Wang 		.ops = &mtk_clk_gate_ops_setclr_inv,	\
51e9862118SShunli Wang 	}
52e9862118SShunli Wang 
53e9862118SShunli Wang static const struct mtk_gate vdec_clks[] = {
54e9862118SShunli Wang 	GATE_VDEC0(CLK_VDEC_CKGEN, "vdec_cken", "vdec_sel", 0),
55e9862118SShunli Wang 	GATE_VDEC1(CLK_VDEC_LARB, "vdec_larb_cken", "mm_sel", 0),
56e9862118SShunli Wang };
57e9862118SShunli Wang 
58e9862118SShunli Wang static const struct of_device_id of_match_clk_mt2701_vdec[] = {
59e9862118SShunli Wang 	{ .compatible = "mediatek,mt2701-vdecsys", },
60e9862118SShunli Wang 	{}
61e9862118SShunli Wang };
62e9862118SShunli Wang 
63e9862118SShunli Wang static int clk_mt2701_vdec_probe(struct platform_device *pdev)
64e9862118SShunli Wang {
65e9862118SShunli Wang 	struct clk_onecell_data *clk_data;
66e9862118SShunli Wang 	int r;
67e9862118SShunli Wang 	struct device_node *node = pdev->dev.of_node;
68e9862118SShunli Wang 
69e9862118SShunli Wang 	clk_data = mtk_alloc_clk_data(CLK_VDEC_NR);
70e9862118SShunli Wang 
71e9862118SShunli Wang 	mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
72e9862118SShunli Wang 						clk_data);
73e9862118SShunli Wang 
74e9862118SShunli Wang 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
75e9862118SShunli Wang 	if (r)
76e9862118SShunli Wang 		dev_err(&pdev->dev,
77e9862118SShunli Wang 			"could not register clock provider: %s: %d\n",
78e9862118SShunli Wang 			pdev->name, r);
79e9862118SShunli Wang 
80e9862118SShunli Wang 	return r;
81e9862118SShunli Wang }
82e9862118SShunli Wang 
83e9862118SShunli Wang static struct platform_driver clk_mt2701_vdec_drv = {
84e9862118SShunli Wang 	.probe = clk_mt2701_vdec_probe,
85e9862118SShunli Wang 	.driver = {
86e9862118SShunli Wang 		.name = "clk-mt2701-vdec",
87e9862118SShunli Wang 		.of_match_table = of_match_clk_mt2701_vdec,
88e9862118SShunli Wang 	},
89e9862118SShunli Wang };
90e9862118SShunli Wang 
91e9862118SShunli Wang builtin_platform_driver(clk_mt2701_vdec_drv);
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