11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2e9862118SShunli Wang /*
3e9862118SShunli Wang  * Copyright (c) 2014 MediaTek Inc.
4e9862118SShunli Wang  * Author: Shunli Wang <shunli.wang@mediatek.com>
5e9862118SShunli Wang  */
6e9862118SShunli Wang 
7e9862118SShunli Wang #include <linux/clk-provider.h>
8e9862118SShunli Wang #include <linux/platform_device.h>
9e9862118SShunli Wang 
10e9862118SShunli Wang #include "clk-mtk.h"
11e9862118SShunli Wang #include "clk-gate.h"
12e9862118SShunli Wang 
13e9862118SShunli Wang #include <dt-bindings/clock/mt2701-clk.h>
14e9862118SShunli Wang 
15e9862118SShunli Wang static const struct mtk_gate_regs vdec0_cg_regs = {
16e9862118SShunli Wang 	.set_ofs = 0x0000,
17e9862118SShunli Wang 	.clr_ofs = 0x0004,
18e9862118SShunli Wang 	.sta_ofs = 0x0000,
19e9862118SShunli Wang };
20e9862118SShunli Wang 
21e9862118SShunli Wang static const struct mtk_gate_regs vdec1_cg_regs = {
22e9862118SShunli Wang 	.set_ofs = 0x0008,
23e9862118SShunli Wang 	.clr_ofs = 0x000c,
24e9862118SShunli Wang 	.sta_ofs = 0x0008,
25e9862118SShunli Wang };
26e9862118SShunli Wang 
27e9862118SShunli Wang #define GATE_VDEC0(_id, _name, _parent, _shift) {	\
28e9862118SShunli Wang 		.id = _id,				\
29e9862118SShunli Wang 		.name = _name,				\
30e9862118SShunli Wang 		.parent_name = _parent,			\
31e9862118SShunli Wang 		.regs = &vdec0_cg_regs,			\
32e9862118SShunli Wang 		.shift = _shift,			\
33e9862118SShunli Wang 		.ops = &mtk_clk_gate_ops_setclr_inv,	\
34e9862118SShunli Wang 	}
35e9862118SShunli Wang 
36e9862118SShunli Wang #define GATE_VDEC1(_id, _name, _parent, _shift) {	\
37e9862118SShunli Wang 		.id = _id,				\
38e9862118SShunli Wang 		.name = _name,				\
39e9862118SShunli Wang 		.parent_name = _parent,			\
40e9862118SShunli Wang 		.regs = &vdec1_cg_regs,			\
41e9862118SShunli Wang 		.shift = _shift,			\
42e9862118SShunli Wang 		.ops = &mtk_clk_gate_ops_setclr_inv,	\
43e9862118SShunli Wang 	}
44e9862118SShunli Wang 
45e9862118SShunli Wang static const struct mtk_gate vdec_clks[] = {
46e9862118SShunli Wang 	GATE_VDEC0(CLK_VDEC_CKGEN, "vdec_cken", "vdec_sel", 0),
47e9862118SShunli Wang 	GATE_VDEC1(CLK_VDEC_LARB, "vdec_larb_cken", "mm_sel", 0),
48e9862118SShunli Wang };
49e9862118SShunli Wang 
50*973d1607SMiles Chen static const struct mtk_clk_desc vdec_desc = {
51*973d1607SMiles Chen 	.clks = vdec_clks,
52*973d1607SMiles Chen 	.num_clks = ARRAY_SIZE(vdec_clks),
53e9862118SShunli Wang };
54e9862118SShunli Wang 
55*973d1607SMiles Chen static const struct of_device_id of_match_clk_mt2701_vdec[] = {
56e9862118SShunli Wang 	{
57*973d1607SMiles Chen 		.compatible = "mediatek,mt2701-vdecsys",
58*973d1607SMiles Chen 		.data = &vdec_desc,
59*973d1607SMiles Chen 	}, {
60*973d1607SMiles Chen 		/* sentinel */
61e9862118SShunli Wang 	}
62*973d1607SMiles Chen };
63e9862118SShunli Wang 
64e9862118SShunli Wang static struct platform_driver clk_mt2701_vdec_drv = {
65*973d1607SMiles Chen 	.probe = mtk_clk_simple_probe,
66*973d1607SMiles Chen 	.remove = mtk_clk_simple_remove,
67e9862118SShunli Wang 	.driver = {
68e9862118SShunli Wang 		.name = "clk-mt2701-vdec",
69e9862118SShunli Wang 		.of_match_table = of_match_clk_mt2701_vdec,
70e9862118SShunli Wang 	},
71e9862118SShunli Wang };
72e9862118SShunli Wang 
73e9862118SShunli Wang builtin_platform_driver(clk_mt2701_vdec_drv);
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