11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2e9862118SShunli Wang /*
3e9862118SShunli Wang  * Copyright (c) 2014 MediaTek Inc.
4e9862118SShunli Wang  * Author: Shunli Wang <shunli.wang@mediatek.com>
5e9862118SShunli Wang  */
6e9862118SShunli Wang 
7e9862118SShunli Wang #include <linux/clk-provider.h>
8e9862118SShunli Wang #include <linux/platform_device.h>
9e9862118SShunli Wang 
10e9862118SShunli Wang #include "clk-mtk.h"
11e9862118SShunli Wang #include "clk-gate.h"
12e9862118SShunli Wang 
13e9862118SShunli Wang #include <dt-bindings/clock/mt2701-clk.h>
14e9862118SShunli Wang 
15e9862118SShunli Wang static const struct mtk_gate_regs vdec0_cg_regs = {
16e9862118SShunli Wang 	.set_ofs = 0x0000,
17e9862118SShunli Wang 	.clr_ofs = 0x0004,
18e9862118SShunli Wang 	.sta_ofs = 0x0000,
19e9862118SShunli Wang };
20e9862118SShunli Wang 
21e9862118SShunli Wang static const struct mtk_gate_regs vdec1_cg_regs = {
22e9862118SShunli Wang 	.set_ofs = 0x0008,
23e9862118SShunli Wang 	.clr_ofs = 0x000c,
24e9862118SShunli Wang 	.sta_ofs = 0x0008,
25e9862118SShunli Wang };
26e9862118SShunli Wang 
27*4c85e20bSAngeloGioacchino Del Regno #define GATE_VDEC0(_id, _name, _parent, _shift)				\
28*4c85e20bSAngeloGioacchino Del Regno 	GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
29e9862118SShunli Wang 
30*4c85e20bSAngeloGioacchino Del Regno #define GATE_VDEC1(_id, _name, _parent, _shift)				\
31*4c85e20bSAngeloGioacchino Del Regno 	GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
32e9862118SShunli Wang 
33e9862118SShunli Wang static const struct mtk_gate vdec_clks[] = {
34e9862118SShunli Wang 	GATE_VDEC0(CLK_VDEC_CKGEN, "vdec_cken", "vdec_sel", 0),
35e9862118SShunli Wang 	GATE_VDEC1(CLK_VDEC_LARB, "vdec_larb_cken", "mm_sel", 0),
36e9862118SShunli Wang };
37e9862118SShunli Wang 
38973d1607SMiles Chen static const struct mtk_clk_desc vdec_desc = {
39973d1607SMiles Chen 	.clks = vdec_clks,
40973d1607SMiles Chen 	.num_clks = ARRAY_SIZE(vdec_clks),
41e9862118SShunli Wang };
42e9862118SShunli Wang 
43973d1607SMiles Chen static const struct of_device_id of_match_clk_mt2701_vdec[] = {
44e9862118SShunli Wang 	{
45973d1607SMiles Chen 		.compatible = "mediatek,mt2701-vdecsys",
46973d1607SMiles Chen 		.data = &vdec_desc,
47973d1607SMiles Chen 	}, {
48973d1607SMiles Chen 		/* sentinel */
49e9862118SShunli Wang 	}
50973d1607SMiles Chen };
51e9862118SShunli Wang 
52e9862118SShunli Wang static struct platform_driver clk_mt2701_vdec_drv = {
53973d1607SMiles Chen 	.probe = mtk_clk_simple_probe,
54973d1607SMiles Chen 	.remove = mtk_clk_simple_remove,
55e9862118SShunli Wang 	.driver = {
56e9862118SShunli Wang 		.name = "clk-mt2701-vdec",
57e9862118SShunli Wang 		.of_match_table = of_match_clk_mt2701_vdec,
58e9862118SShunli Wang 	},
59e9862118SShunli Wang };
60e9862118SShunli Wang 
61e9862118SShunli Wang builtin_platform_driver(clk_mt2701_vdec_drv);
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