11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e9862118SShunli Wang /* 3e9862118SShunli Wang * Copyright (c) 2014 MediaTek Inc. 4e9862118SShunli Wang * Author: Shunli Wang <shunli.wang@mediatek.com> 5e9862118SShunli Wang */ 6e9862118SShunli Wang 7e9862118SShunli Wang #include <linux/clk-provider.h> 8e9862118SShunli Wang #include <linux/platform_device.h> 9e9862118SShunli Wang 10e9862118SShunli Wang #include "clk-mtk.h" 11e9862118SShunli Wang #include "clk-gate.h" 12e9862118SShunli Wang 13e9862118SShunli Wang #include <dt-bindings/clock/mt2701-clk.h> 14e9862118SShunli Wang 15e9862118SShunli Wang static const struct mtk_gate_regs vdec0_cg_regs = { 16e9862118SShunli Wang .set_ofs = 0x0000, 17e9862118SShunli Wang .clr_ofs = 0x0004, 18e9862118SShunli Wang .sta_ofs = 0x0000, 19e9862118SShunli Wang }; 20e9862118SShunli Wang 21e9862118SShunli Wang static const struct mtk_gate_regs vdec1_cg_regs = { 22e9862118SShunli Wang .set_ofs = 0x0008, 23e9862118SShunli Wang .clr_ofs = 0x000c, 24e9862118SShunli Wang .sta_ofs = 0x0008, 25e9862118SShunli Wang }; 26e9862118SShunli Wang 27e9862118SShunli Wang #define GATE_VDEC0(_id, _name, _parent, _shift) { \ 28e9862118SShunli Wang .id = _id, \ 29e9862118SShunli Wang .name = _name, \ 30e9862118SShunli Wang .parent_name = _parent, \ 31e9862118SShunli Wang .regs = &vdec0_cg_regs, \ 32e9862118SShunli Wang .shift = _shift, \ 33e9862118SShunli Wang .ops = &mtk_clk_gate_ops_setclr_inv, \ 34e9862118SShunli Wang } 35e9862118SShunli Wang 36e9862118SShunli Wang #define GATE_VDEC1(_id, _name, _parent, _shift) { \ 37e9862118SShunli Wang .id = _id, \ 38e9862118SShunli Wang .name = _name, \ 39e9862118SShunli Wang .parent_name = _parent, \ 40e9862118SShunli Wang .regs = &vdec1_cg_regs, \ 41e9862118SShunli Wang .shift = _shift, \ 42e9862118SShunli Wang .ops = &mtk_clk_gate_ops_setclr_inv, \ 43e9862118SShunli Wang } 44e9862118SShunli Wang 45e9862118SShunli Wang static const struct mtk_gate vdec_clks[] = { 46e9862118SShunli Wang GATE_VDEC0(CLK_VDEC_CKGEN, "vdec_cken", "vdec_sel", 0), 47e9862118SShunli Wang GATE_VDEC1(CLK_VDEC_LARB, "vdec_larb_cken", "mm_sel", 0), 48e9862118SShunli Wang }; 49e9862118SShunli Wang 50e9862118SShunli Wang static const struct of_device_id of_match_clk_mt2701_vdec[] = { 51e9862118SShunli Wang { .compatible = "mediatek,mt2701-vdecsys", }, 52e9862118SShunli Wang {} 53e9862118SShunli Wang }; 54e9862118SShunli Wang 55e9862118SShunli Wang static int clk_mt2701_vdec_probe(struct platform_device *pdev) 56e9862118SShunli Wang { 57e9862118SShunli Wang struct clk_onecell_data *clk_data; 58e9862118SShunli Wang int r; 59e9862118SShunli Wang struct device_node *node = pdev->dev.of_node; 60e9862118SShunli Wang 61e9862118SShunli Wang clk_data = mtk_alloc_clk_data(CLK_VDEC_NR); 62e9862118SShunli Wang 63e9862118SShunli Wang mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), 64e9862118SShunli Wang clk_data); 65e9862118SShunli Wang 66e9862118SShunli Wang r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 67e9862118SShunli Wang if (r) 68e9862118SShunli Wang dev_err(&pdev->dev, 69e9862118SShunli Wang "could not register clock provider: %s: %d\n", 70e9862118SShunli Wang pdev->name, r); 71e9862118SShunli Wang 72e9862118SShunli Wang return r; 73e9862118SShunli Wang } 74e9862118SShunli Wang 75e9862118SShunli Wang static struct platform_driver clk_mt2701_vdec_drv = { 76e9862118SShunli Wang .probe = clk_mt2701_vdec_probe, 77e9862118SShunli Wang .driver = { 78e9862118SShunli Wang .name = "clk-mt2701-vdec", 79e9862118SShunli Wang .of_match_table = of_match_clk_mt2701_vdec, 80e9862118SShunli Wang }, 81e9862118SShunli Wang }; 82e9862118SShunli Wang 83e9862118SShunli Wang builtin_platform_driver(clk_mt2701_vdec_drv); 84