11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e9862118SShunli Wang /* 3e9862118SShunli Wang * Copyright (c) 2014 MediaTek Inc. 4e9862118SShunli Wang * Author: Shunli Wang <shunli.wang@mediatek.com> 5e9862118SShunli Wang */ 6e9862118SShunli Wang 7e9862118SShunli Wang #include <linux/clk-provider.h> 8e9862118SShunli Wang #include <linux/platform_device.h> 9e9862118SShunli Wang 10e9862118SShunli Wang #include "clk-mtk.h" 11e9862118SShunli Wang #include "clk-gate.h" 12e9862118SShunli Wang 13e9862118SShunli Wang #include <dt-bindings/clock/mt2701-clk.h> 14e9862118SShunli Wang 15e9862118SShunli Wang static const struct mtk_gate_regs disp0_cg_regs = { 16e9862118SShunli Wang .set_ofs = 0x0104, 17e9862118SShunli Wang .clr_ofs = 0x0108, 18e9862118SShunli Wang .sta_ofs = 0x0100, 19e9862118SShunli Wang }; 20e9862118SShunli Wang 21e9862118SShunli Wang static const struct mtk_gate_regs disp1_cg_regs = { 22e9862118SShunli Wang .set_ofs = 0x0114, 23e9862118SShunli Wang .clr_ofs = 0x0118, 24e9862118SShunli Wang .sta_ofs = 0x0110, 25e9862118SShunli Wang }; 26e9862118SShunli Wang 27e9862118SShunli Wang #define GATE_DISP0(_id, _name, _parent, _shift) { \ 28e9862118SShunli Wang .id = _id, \ 29e9862118SShunli Wang .name = _name, \ 30e9862118SShunli Wang .parent_name = _parent, \ 31e9862118SShunli Wang .regs = &disp0_cg_regs, \ 32e9862118SShunli Wang .shift = _shift, \ 33e9862118SShunli Wang .ops = &mtk_clk_gate_ops_setclr, \ 34e9862118SShunli Wang } 35e9862118SShunli Wang 36e9862118SShunli Wang #define GATE_DISP1(_id, _name, _parent, _shift) { \ 37e9862118SShunli Wang .id = _id, \ 38e9862118SShunli Wang .name = _name, \ 39e9862118SShunli Wang .parent_name = _parent, \ 40e9862118SShunli Wang .regs = &disp1_cg_regs, \ 41e9862118SShunli Wang .shift = _shift, \ 42e9862118SShunli Wang .ops = &mtk_clk_gate_ops_setclr, \ 43e9862118SShunli Wang } 44e9862118SShunli Wang 45e9862118SShunli Wang static const struct mtk_gate mm_clks[] = { 46e9862118SShunli Wang GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0), 47e9862118SShunli Wang GATE_DISP0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), 48e9862118SShunli Wang GATE_DISP0(CLK_MM_CMDQ, "mm_cmdq", "mm_sel", 2), 49e9862118SShunli Wang GATE_DISP0(CLK_MM_MUTEX, "mm_mutex", "mm_sel", 3), 50e9862118SShunli Wang GATE_DISP0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 4), 51e9862118SShunli Wang GATE_DISP0(CLK_MM_DISP_BLS, "mm_disp_bls", "mm_sel", 5), 52e9862118SShunli Wang GATE_DISP0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "mm_sel", 6), 53e9862118SShunli Wang GATE_DISP0(CLK_MM_DISP_RDMA, "mm_disp_rdma", "mm_sel", 7), 54e9862118SShunli Wang GATE_DISP0(CLK_MM_DISP_OVL, "mm_disp_ovl", "mm_sel", 8), 55e9862118SShunli Wang GATE_DISP0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9), 56e9862118SShunli Wang GATE_DISP0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "mm_sel", 10), 57e9862118SShunli Wang GATE_DISP0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11), 58e9862118SShunli Wang GATE_DISP0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 12), 59e9862118SShunli Wang GATE_DISP0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 13), 60e9862118SShunli Wang GATE_DISP0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "mm_sel", 14), 61e9862118SShunli Wang GATE_DISP0(CLK_MM_MDP_BLS_26M, "mm_mdp_bls_26m", "pwm_sel", 15), 62e9862118SShunli Wang GATE_DISP0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 16), 63e9862118SShunli Wang GATE_DISP0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 17), 64e9862118SShunli Wang GATE_DISP0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 18), 65e9862118SShunli Wang GATE_DISP0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19), 66e9862118SShunli Wang GATE_DISP0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 20), 67e9862118SShunli Wang GATE_DISP1(CLK_MM_DSI_ENGINE, "mm_dsi_eng", "mm_sel", 0), 68e9862118SShunli Wang GATE_DISP1(CLK_MM_DSI_DIG, "mm_dsi_dig", "dsi0_lntc_dsi", 1), 69e9862118SShunli Wang GATE_DISP1(CLK_MM_DPI_DIGL, "mm_dpi_digl", "dpi0_sel", 2), 70e9862118SShunli Wang GATE_DISP1(CLK_MM_DPI_ENGINE, "mm_dpi_eng", "mm_sel", 3), 71e9862118SShunli Wang GATE_DISP1(CLK_MM_DPI1_DIGL, "mm_dpi1_digl", "dpi1_sel", 4), 72e9862118SShunli Wang GATE_DISP1(CLK_MM_DPI1_ENGINE, "mm_dpi1_eng", "mm_sel", 5), 73e9862118SShunli Wang GATE_DISP1(CLK_MM_TVE_OUTPUT, "mm_tve_output", "tve_sel", 6), 74e9862118SShunli Wang GATE_DISP1(CLK_MM_TVE_INPUT, "mm_tve_input", "dpi0_sel", 7), 75e9862118SShunli Wang GATE_DISP1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi1_sel", 8), 76e9862118SShunli Wang GATE_DISP1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmi_sel", 9), 77e9862118SShunli Wang GATE_DISP1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll_sel", 10), 78e9862118SShunli Wang GATE_DISP1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll_sel", 11), 79e9862118SShunli Wang GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14), 80e9862118SShunli Wang }; 81e9862118SShunli Wang 82*65c10c50SAngeloGioacchino Del Regno static const struct mtk_clk_desc mm_desc = { 83*65c10c50SAngeloGioacchino Del Regno .clks = mm_clks, 84*65c10c50SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(mm_clks), 85*65c10c50SAngeloGioacchino Del Regno }; 86e9862118SShunli Wang 87*65c10c50SAngeloGioacchino Del Regno static const struct platform_device_id clk_mt2701_mm_id_table[] = { 88*65c10c50SAngeloGioacchino Del Regno { .name = "clk-mt2701-mm", .driver_data = (kernel_ulong_t)&mm_desc }, 89*65c10c50SAngeloGioacchino Del Regno { /* sentinel */ } 90*65c10c50SAngeloGioacchino Del Regno }; 91e9862118SShunli Wang 92e9862118SShunli Wang static struct platform_driver clk_mt2701_mm_drv = { 93*65c10c50SAngeloGioacchino Del Regno .probe = mtk_clk_pdev_probe, 94*65c10c50SAngeloGioacchino Del Regno .remove = mtk_clk_pdev_remove, 95e9862118SShunli Wang .driver = { 96e9862118SShunli Wang .name = "clk-mt2701-mm", 97e9862118SShunli Wang }, 98*65c10c50SAngeloGioacchino Del Regno .id_table = clk_mt2701_mm_id_table, 99e9862118SShunli Wang }; 100e9862118SShunli Wang 101e9862118SShunli Wang builtin_platform_driver(clk_mt2701_mm_drv); 102