11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2e9862118SShunli Wang /*
3e9862118SShunli Wang  * Copyright (c) 2014 MediaTek Inc.
4e9862118SShunli Wang  * Author: Shunli Wang <shunli.wang@mediatek.com>
5e9862118SShunli Wang  */
6e9862118SShunli Wang 
7e9862118SShunli Wang #include <linux/clk-provider.h>
8e9862118SShunli Wang #include <linux/platform_device.h>
9e9862118SShunli Wang 
10e9862118SShunli Wang #include "clk-mtk.h"
11e9862118SShunli Wang #include "clk-gate.h"
12e9862118SShunli Wang 
13e9862118SShunli Wang #include <dt-bindings/clock/mt2701-clk.h>
14e9862118SShunli Wang 
15e9862118SShunli Wang static const struct mtk_gate_regs img_cg_regs = {
16e9862118SShunli Wang 	.set_ofs = 0x0004,
17e9862118SShunli Wang 	.clr_ofs = 0x0008,
18e9862118SShunli Wang 	.sta_ofs = 0x0000,
19e9862118SShunli Wang };
20e9862118SShunli Wang 
21e9862118SShunli Wang #define GATE_IMG(_id, _name, _parent, _shift) {		\
22e9862118SShunli Wang 		.id = _id,				\
23e9862118SShunli Wang 		.name = _name,				\
24e9862118SShunli Wang 		.parent_name = _parent,			\
25e9862118SShunli Wang 		.regs = &img_cg_regs,			\
26e9862118SShunli Wang 		.shift = _shift,			\
27e9862118SShunli Wang 		.ops = &mtk_clk_gate_ops_setclr,	\
28e9862118SShunli Wang 	}
29e9862118SShunli Wang 
30e9862118SShunli Wang static const struct mtk_gate img_clks[] = {
31e9862118SShunli Wang 	GATE_IMG(CLK_IMG_SMI_COMM, "img_smi_comm", "mm_sel", 0),
32e9862118SShunli Wang 	GATE_IMG(CLK_IMG_RESZ, "img_resz", "mm_sel", 1),
33e9862118SShunli Wang 	GATE_IMG(CLK_IMG_JPGDEC_SMI, "img_jpgdec_smi", "mm_sel", 5),
34e9862118SShunli Wang 	GATE_IMG(CLK_IMG_JPGDEC, "img_jpgdec", "mm_sel", 6),
35e9862118SShunli Wang 	GATE_IMG(CLK_IMG_VENC_LT, "img_venc_lt", "mm_sel", 8),
36e9862118SShunli Wang 	GATE_IMG(CLK_IMG_VENC, "img_venc", "mm_sel", 9),
37e9862118SShunli Wang };
38e9862118SShunli Wang 
39e9862118SShunli Wang static const struct of_device_id of_match_clk_mt2701_img[] = {
40e9862118SShunli Wang 	{ .compatible = "mediatek,mt2701-imgsys", },
41e9862118SShunli Wang 	{}
42e9862118SShunli Wang };
43e9862118SShunli Wang 
44e9862118SShunli Wang static int clk_mt2701_img_probe(struct platform_device *pdev)
45e9862118SShunli Wang {
46e9862118SShunli Wang 	struct clk_onecell_data *clk_data;
47e9862118SShunli Wang 	int r;
48e9862118SShunli Wang 	struct device_node *node = pdev->dev.of_node;
49e9862118SShunli Wang 
50e9862118SShunli Wang 	clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
51e9862118SShunli Wang 
52e9862118SShunli Wang 	mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
53e9862118SShunli Wang 						clk_data);
54e9862118SShunli Wang 
55e9862118SShunli Wang 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
56e9862118SShunli Wang 	if (r)
57e9862118SShunli Wang 		dev_err(&pdev->dev,
58e9862118SShunli Wang 			"could not register clock provider: %s: %d\n",
59e9862118SShunli Wang 			pdev->name, r);
60e9862118SShunli Wang 
61e9862118SShunli Wang 	return r;
62e9862118SShunli Wang }
63e9862118SShunli Wang 
64e9862118SShunli Wang static struct platform_driver clk_mt2701_img_drv = {
65e9862118SShunli Wang 	.probe = clk_mt2701_img_probe,
66e9862118SShunli Wang 	.driver = {
67e9862118SShunli Wang 		.name = "clk-mt2701-img",
68e9862118SShunli Wang 		.of_match_table = of_match_clk_mt2701_img,
69e9862118SShunli Wang 	},
70e9862118SShunli Wang };
71e9862118SShunli Wang 
72e9862118SShunli Wang builtin_platform_driver(clk_mt2701_img_drv);
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