1 /*
2  * Copyright (c) 2014 MediaTek Inc.
3  * Author: Shunli Wang <shunli.wang@mediatek.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  */
14 
15 #include <linux/clk-provider.h>
16 #include <linux/platform_device.h>
17 
18 #include "clk-mtk.h"
19 #include "clk-gate.h"
20 
21 #include <dt-bindings/clock/mt2701-clk.h>
22 
23 static const struct mtk_gate_regs hif_cg_regs = {
24 	.sta_ofs = 0x0030,
25 };
26 
27 #define GATE_HIF(_id, _name, _parent, _shift) {		\
28 		.id = _id,				\
29 		.name = _name,				\
30 		.parent_name = _parent,			\
31 		.regs = &hif_cg_regs,			\
32 		.shift = _shift,			\
33 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
34 	}
35 
36 static const struct mtk_gate hif_clks[] = {
37 	GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
38 	GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
39 	GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
40 	GATE_HIF(CLK_HIFSYS_PCIE1, "pcie1_clk", "ethpll_500m_ck", 25),
41 	GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
42 };
43 
44 static const struct of_device_id of_match_clk_mt2701_hif[] = {
45 	{ .compatible = "mediatek,mt2701-hifsys", },
46 	{}
47 };
48 
49 static int clk_mt2701_hif_probe(struct platform_device *pdev)
50 {
51 	struct clk_onecell_data *clk_data;
52 	int r;
53 	struct device_node *node = pdev->dev.of_node;
54 
55 	clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
56 
57 	mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
58 						clk_data);
59 
60 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
61 	if (r) {
62 		dev_err(&pdev->dev,
63 			"could not register clock provider: %s: %d\n",
64 			pdev->name, r);
65 		return r;
66 	}
67 
68 	mtk_register_reset_controller(node, 1, 0x34);
69 
70 	return 0;
71 }
72 
73 static struct platform_driver clk_mt2701_hif_drv = {
74 	.probe = clk_mt2701_hif_probe,
75 	.driver = {
76 		.name = "clk-mt2701-hif",
77 		.of_match_table = of_match_clk_mt2701_hif,
78 	},
79 };
80 
81 builtin_platform_driver(clk_mt2701_hif_drv);
82