11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2e9862118SShunli Wang /*
3e9862118SShunli Wang  * Copyright (c) 2014 MediaTek Inc.
4e9862118SShunli Wang  * Author: Shunli Wang <shunli.wang@mediatek.com>
5e9862118SShunli Wang  */
6e9862118SShunli Wang 
7e9862118SShunli Wang #include <linux/clk-provider.h>
8e9862118SShunli Wang #include <linux/platform_device.h>
9e9862118SShunli Wang 
10e9862118SShunli Wang #include "clk-mtk.h"
11e9862118SShunli Wang #include "clk-gate.h"
12e9862118SShunli Wang 
13e9862118SShunli Wang #include <dt-bindings/clock/mt2701-clk.h>
14e9862118SShunli Wang 
15e9862118SShunli Wang static const struct mtk_gate_regs hif_cg_regs = {
16e9862118SShunli Wang 	.sta_ofs = 0x0030,
17e9862118SShunli Wang };
18e9862118SShunli Wang 
19e9862118SShunli Wang #define GATE_HIF(_id, _name, _parent, _shift) {		\
20e9862118SShunli Wang 		.id = _id,				\
21e9862118SShunli Wang 		.name = _name,				\
22e9862118SShunli Wang 		.parent_name = _parent,			\
23e9862118SShunli Wang 		.regs = &hif_cg_regs,			\
24e9862118SShunli Wang 		.shift = _shift,			\
25e9862118SShunli Wang 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
26e9862118SShunli Wang 	}
27e9862118SShunli Wang 
28e9862118SShunli Wang static const struct mtk_gate hif_clks[] = {
29e9862118SShunli Wang 	GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
30e9862118SShunli Wang 	GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
31e9862118SShunli Wang 	GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
32e9862118SShunli Wang 	GATE_HIF(CLK_HIFSYS_PCIE1, "pcie1_clk", "ethpll_500m_ck", 25),
33e9862118SShunli Wang 	GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
34e9862118SShunli Wang };
35e9862118SShunli Wang 
36*723e3671SRex-BC Chen static u16 rst_ofs[] = { 0x34, };
37*723e3671SRex-BC Chen 
382d2a2900SRex-BC Chen static const struct mtk_clk_rst_desc clk_rst_desc = {
392d2a2900SRex-BC Chen 	.version = MTK_RST_SIMPLE,
40*723e3671SRex-BC Chen 	.rst_bank_ofs = rst_ofs,
41*723e3671SRex-BC Chen 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
422d2a2900SRex-BC Chen };
432d2a2900SRex-BC Chen 
44e9862118SShunli Wang static const struct of_device_id of_match_clk_mt2701_hif[] = {
45e9862118SShunli Wang 	{ .compatible = "mediatek,mt2701-hifsys", },
46e9862118SShunli Wang 	{}
47e9862118SShunli Wang };
48e9862118SShunli Wang 
49e9862118SShunli Wang static int clk_mt2701_hif_probe(struct platform_device *pdev)
50e9862118SShunli Wang {
51609cc5e1SChen-Yu Tsai 	struct clk_hw_onecell_data *clk_data;
52e9862118SShunli Wang 	int r;
53e9862118SShunli Wang 	struct device_node *node = pdev->dev.of_node;
54e9862118SShunli Wang 
55e9862118SShunli Wang 	clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
56e9862118SShunli Wang 
57e9862118SShunli Wang 	mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
58e9862118SShunli Wang 						clk_data);
59e9862118SShunli Wang 
60609cc5e1SChen-Yu Tsai 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
618c1ee96aSShunli Wang 	if (r) {
62e9862118SShunli Wang 		dev_err(&pdev->dev,
63e9862118SShunli Wang 			"could not register clock provider: %s: %d\n",
64e9862118SShunli Wang 			pdev->name, r);
65e9862118SShunli Wang 		return r;
66e9862118SShunli Wang 	}
67e9862118SShunli Wang 
682d2a2900SRex-BC Chen 	mtk_register_reset_controller(node, &clk_rst_desc);
698c1ee96aSShunli Wang 
708c1ee96aSShunli Wang 	return 0;
718c1ee96aSShunli Wang }
728c1ee96aSShunli Wang 
73e9862118SShunli Wang static struct platform_driver clk_mt2701_hif_drv = {
74e9862118SShunli Wang 	.probe = clk_mt2701_hif_probe,
75e9862118SShunli Wang 	.driver = {
76e9862118SShunli Wang 		.name = "clk-mt2701-hif",
77e9862118SShunli Wang 		.of_match_table = of_match_clk_mt2701_hif,
78e9862118SShunli Wang 	},
79e9862118SShunli Wang };
80e9862118SShunli Wang 
81e9862118SShunli Wang builtin_platform_driver(clk_mt2701_hif_drv);
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