1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014 MediaTek Inc.
4  * Author: Shunli Wang <shunli.wang@mediatek.com>
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/platform_device.h>
9 
10 #include "clk-mtk.h"
11 #include "clk-gate.h"
12 
13 #include <dt-bindings/clock/mt2701-clk.h>
14 
15 static const struct mtk_gate_regs eth_cg_regs = {
16 	.sta_ofs = 0x0030,
17 };
18 
19 #define GATE_ETH(_id, _name, _parent, _shift) {		\
20 		.id = _id,				\
21 		.name = _name,				\
22 		.parent_name = _parent,			\
23 		.regs = &eth_cg_regs,			\
24 		.shift = _shift,			\
25 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
26 	}
27 
28 static const struct mtk_gate eth_clks[] = {
29 	GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
30 	GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
31 	GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
32 	GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),
33 	GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11),
34 	GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14),
35 	GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17),
36 	GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
37 };
38 
39 static const struct of_device_id of_match_clk_mt2701_eth[] = {
40 	{ .compatible = "mediatek,mt2701-ethsys", },
41 	{}
42 };
43 
44 static int clk_mt2701_eth_probe(struct platform_device *pdev)
45 {
46 	struct clk_onecell_data *clk_data;
47 	int r;
48 	struct device_node *node = pdev->dev.of_node;
49 
50 	clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
51 
52 	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
53 						clk_data);
54 
55 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
56 	if (r)
57 		dev_err(&pdev->dev,
58 			"could not register clock provider: %s: %d\n",
59 			pdev->name, r);
60 
61 	mtk_register_reset_controller(node, 1, 0x34);
62 
63 	return r;
64 }
65 
66 static struct platform_driver clk_mt2701_eth_drv = {
67 	.probe = clk_mt2701_eth_probe,
68 	.driver = {
69 		.name = "clk-mt2701-eth",
70 		.of_match_table = of_match_clk_mt2701_eth,
71 	},
72 };
73 
74 builtin_platform_driver(clk_mt2701_eth_drv);
75