1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014 MediaTek Inc.
4  * Author: Shunli Wang <shunli.wang@mediatek.com>
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/platform_device.h>
9 
10 #include "clk-mtk.h"
11 #include "clk-gate.h"
12 
13 #include <dt-bindings/clock/mt2701-clk.h>
14 
15 static const struct mtk_gate_regs eth_cg_regs = {
16 	.sta_ofs = 0x0030,
17 };
18 
19 #define GATE_ETH(_id, _name, _parent, _shift) {		\
20 		.id = _id,				\
21 		.name = _name,				\
22 		.parent_name = _parent,			\
23 		.regs = &eth_cg_regs,			\
24 		.shift = _shift,			\
25 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
26 	}
27 
28 static const struct mtk_gate eth_clks[] = {
29 	GATE_DUMMY(CLK_DUMMY, "eth_dummy"),
30 	GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
31 	GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
32 	GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
33 	GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),
34 	GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11),
35 	GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14),
36 	GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17),
37 	GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
38 };
39 
40 static u16 rst_ofs[] = { 0x34, };
41 
42 static const struct mtk_clk_rst_desc clk_rst_desc = {
43 	.version = MTK_RST_SIMPLE,
44 	.rst_bank_ofs = rst_ofs,
45 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
46 };
47 
48 static const struct mtk_clk_desc eth_desc = {
49 	.clks = eth_clks,
50 	.num_clks = ARRAY_SIZE(eth_clks),
51 	.rst_desc = &clk_rst_desc,
52 };
53 
54 static const struct of_device_id of_match_clk_mt2701_eth[] = {
55 	{ .compatible = "mediatek,mt2701-ethsys", .data = &eth_desc },
56 	{ /* sentinel */ }
57 };
58 
59 static struct platform_driver clk_mt2701_eth_drv = {
60 	.probe = mtk_clk_simple_probe,
61 	.remove = mtk_clk_simple_remove,
62 	.driver = {
63 		.name = "clk-mt2701-eth",
64 		.of_match_table = of_match_clk_mt2701_eth,
65 	},
66 };
67 
68 builtin_platform_driver(clk_mt2701_eth_drv);
69