11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e9862118SShunli Wang /* 3e9862118SShunli Wang * Copyright (c) 2014 MediaTek Inc. 4e9862118SShunli Wang * Author: Shunli Wang <shunli.wang@mediatek.com> 5e9862118SShunli Wang */ 6e9862118SShunli Wang 7e9862118SShunli Wang #include <linux/clk-provider.h> 8e9862118SShunli Wang #include <linux/platform_device.h> 9e9862118SShunli Wang 10e9862118SShunli Wang #include "clk-mtk.h" 11e9862118SShunli Wang #include "clk-gate.h" 12e9862118SShunli Wang 13e9862118SShunli Wang #include <dt-bindings/clock/mt2701-clk.h> 14e9862118SShunli Wang 15e9862118SShunli Wang static const struct mtk_gate_regs eth_cg_regs = { 16e9862118SShunli Wang .sta_ofs = 0x0030, 17e9862118SShunli Wang }; 18e9862118SShunli Wang 19e9862118SShunli Wang #define GATE_ETH(_id, _name, _parent, _shift) { \ 20e9862118SShunli Wang .id = _id, \ 21e9862118SShunli Wang .name = _name, \ 22e9862118SShunli Wang .parent_name = _parent, \ 23e9862118SShunli Wang .regs = ð_cg_regs, \ 24e9862118SShunli Wang .shift = _shift, \ 25e9862118SShunli Wang .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 26e9862118SShunli Wang } 27e9862118SShunli Wang 28e9862118SShunli Wang static const struct mtk_gate eth_clks[] = { 29e9862118SShunli Wang GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5), 30e9862118SShunli Wang GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6), 31e9862118SShunli Wang GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7), 32e9862118SShunli Wang GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8), 33e9862118SShunli Wang GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11), 34e9862118SShunli Wang GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14), 35e9862118SShunli Wang GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17), 36e9862118SShunli Wang GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29), 37e9862118SShunli Wang }; 38e9862118SShunli Wang 39*2d2a2900SRex-BC Chen static const struct mtk_clk_rst_desc clk_rst_desc = { 40*2d2a2900SRex-BC Chen .version = MTK_RST_SIMPLE, 41*2d2a2900SRex-BC Chen .rst_bank_nr = 1, 42*2d2a2900SRex-BC Chen .reg_ofs = 0x34, 43*2d2a2900SRex-BC Chen }; 44*2d2a2900SRex-BC Chen 45e9862118SShunli Wang static const struct of_device_id of_match_clk_mt2701_eth[] = { 46e9862118SShunli Wang { .compatible = "mediatek,mt2701-ethsys", }, 47e9862118SShunli Wang {} 48e9862118SShunli Wang }; 49e9862118SShunli Wang 50e9862118SShunli Wang static int clk_mt2701_eth_probe(struct platform_device *pdev) 51e9862118SShunli Wang { 52609cc5e1SChen-Yu Tsai struct clk_hw_onecell_data *clk_data; 53e9862118SShunli Wang int r; 54e9862118SShunli Wang struct device_node *node = pdev->dev.of_node; 55e9862118SShunli Wang 56e9862118SShunli Wang clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); 57e9862118SShunli Wang 58e9862118SShunli Wang mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), 59e9862118SShunli Wang clk_data); 60e9862118SShunli Wang 61609cc5e1SChen-Yu Tsai r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 62e9862118SShunli Wang if (r) 63e9862118SShunli Wang dev_err(&pdev->dev, 64e9862118SShunli Wang "could not register clock provider: %s: %d\n", 65e9862118SShunli Wang pdev->name, r); 66e9862118SShunli Wang 67*2d2a2900SRex-BC Chen mtk_register_reset_controller(node, &clk_rst_desc); 68db9c4a1eSJohn Crispin 69e9862118SShunli Wang return r; 70e9862118SShunli Wang } 71e9862118SShunli Wang 72e9862118SShunli Wang static struct platform_driver clk_mt2701_eth_drv = { 73e9862118SShunli Wang .probe = clk_mt2701_eth_probe, 74e9862118SShunli Wang .driver = { 75e9862118SShunli Wang .name = "clk-mt2701-eth", 76e9862118SShunli Wang .of_match_table = of_match_clk_mt2701_eth, 77e9862118SShunli Wang }, 78e9862118SShunli Wang }; 79e9862118SShunli Wang 80e9862118SShunli Wang builtin_platform_driver(clk_mt2701_eth_drv); 81