1e9862118SShunli Wang /* 2e9862118SShunli Wang * Copyright (c) 2014 MediaTek Inc. 3e9862118SShunli Wang * Author: Shunli Wang <shunli.wang@mediatek.com> 4e9862118SShunli Wang * 5e9862118SShunli Wang * This program is free software; you can redistribute it and/or modify 6e9862118SShunli Wang * it under the terms of the GNU General Public License version 2 as 7e9862118SShunli Wang * published by the Free Software Foundation. 8e9862118SShunli Wang * 9e9862118SShunli Wang * This program is distributed in the hope that it will be useful, 10e9862118SShunli Wang * but WITHOUT ANY WARRANTY; without even the implied warranty of 11e9862118SShunli Wang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12e9862118SShunli Wang * GNU General Public License for more details. 13e9862118SShunli Wang */ 14e9862118SShunli Wang 15e9862118SShunli Wang #include <linux/clk-provider.h> 16e9862118SShunli Wang #include <linux/platform_device.h> 17e9862118SShunli Wang 18e9862118SShunli Wang #include "clk-mtk.h" 19e9862118SShunli Wang #include "clk-gate.h" 20e9862118SShunli Wang 21e9862118SShunli Wang #include <dt-bindings/clock/mt2701-clk.h> 22e9862118SShunli Wang 23e9862118SShunli Wang static const struct mtk_gate_regs bdp0_cg_regs = { 24e9862118SShunli Wang .set_ofs = 0x0104, 25e9862118SShunli Wang .clr_ofs = 0x0108, 26e9862118SShunli Wang .sta_ofs = 0x0100, 27e9862118SShunli Wang }; 28e9862118SShunli Wang 29e9862118SShunli Wang static const struct mtk_gate_regs bdp1_cg_regs = { 30e9862118SShunli Wang .set_ofs = 0x0114, 31e9862118SShunli Wang .clr_ofs = 0x0118, 32e9862118SShunli Wang .sta_ofs = 0x0110, 33e9862118SShunli Wang }; 34e9862118SShunli Wang 35e9862118SShunli Wang #define GATE_BDP0(_id, _name, _parent, _shift) { \ 36e9862118SShunli Wang .id = _id, \ 37e9862118SShunli Wang .name = _name, \ 38e9862118SShunli Wang .parent_name = _parent, \ 39e9862118SShunli Wang .regs = &bdp0_cg_regs, \ 40e9862118SShunli Wang .shift = _shift, \ 41e9862118SShunli Wang .ops = &mtk_clk_gate_ops_setclr_inv, \ 42e9862118SShunli Wang } 43e9862118SShunli Wang 44e9862118SShunli Wang #define GATE_BDP1(_id, _name, _parent, _shift) { \ 45e9862118SShunli Wang .id = _id, \ 46e9862118SShunli Wang .name = _name, \ 47e9862118SShunli Wang .parent_name = _parent, \ 48e9862118SShunli Wang .regs = &bdp1_cg_regs, \ 49e9862118SShunli Wang .shift = _shift, \ 50e9862118SShunli Wang .ops = &mtk_clk_gate_ops_setclr_inv, \ 51e9862118SShunli Wang } 52e9862118SShunli Wang 53e9862118SShunli Wang static const struct mtk_gate bdp_clks[] = { 54e9862118SShunli Wang GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0), 55e9862118SShunli Wang GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1), 56e9862118SShunli Wang GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2), 57e9862118SShunli Wang GATE_BDP0(CLK_BDP_WR_VDI_PXL, "wr_vdi_pxl", "hdmi_0_deep340m", 3), 58e9862118SShunli Wang GATE_BDP0(CLK_BDP_WR_VDI_DRAM, "wr_vdi_dram", "mm_sel", 4), 59e9862118SShunli Wang GATE_BDP0(CLK_BDP_WR_B, "wr_bclk", "mm_sel", 5), 60e9862118SShunli Wang GATE_BDP0(CLK_BDP_DGI_IN, "dgi_in", "dpi1_sel", 6), 61e9862118SShunli Wang GATE_BDP0(CLK_BDP_DGI_OUT, "dgi_out", "dpi1_sel", 7), 62e9862118SShunli Wang GATE_BDP0(CLK_BDP_FMT_MAST_27, "fmt_mast_27", "dpi1_sel", 8), 63e9862118SShunli Wang GATE_BDP0(CLK_BDP_FMT_B, "fmt_bclk", "mm_sel", 9), 64e9862118SShunli Wang GATE_BDP0(CLK_BDP_OSD_B, "osd_bclk", "mm_sel", 10), 65e9862118SShunli Wang GATE_BDP0(CLK_BDP_OSD_DRAM, "osd_dram", "mm_sel", 11), 66e9862118SShunli Wang GATE_BDP0(CLK_BDP_OSD_AGENT, "osd_agent", "osd_sel", 12), 67e9862118SShunli Wang GATE_BDP0(CLK_BDP_OSD_PXL, "osd_pxl", "dpi1_sel", 13), 68e9862118SShunli Wang GATE_BDP0(CLK_BDP_RLE_B, "rle_bclk", "mm_sel", 14), 69e9862118SShunli Wang GATE_BDP0(CLK_BDP_RLE_AGENT, "rle_agent", "mm_sel", 15), 70e9862118SShunli Wang GATE_BDP0(CLK_BDP_RLE_DRAM, "rle_dram", "mm_sel", 16), 71e9862118SShunli Wang GATE_BDP0(CLK_BDP_F27M, "f27m", "di_sel", 17), 72e9862118SShunli Wang GATE_BDP0(CLK_BDP_F27M_VDOUT, "f27m_vdout", "di_sel", 18), 73e9862118SShunli Wang GATE_BDP0(CLK_BDP_F27_74_74, "f27_74_74", "di_sel", 19), 74e9862118SShunli Wang GATE_BDP0(CLK_BDP_F2FS, "f2fs", "di_sel", 20), 75e9862118SShunli Wang GATE_BDP0(CLK_BDP_F2FS74_148, "f2fs74_148", "di_sel", 21), 76e9862118SShunli Wang GATE_BDP0(CLK_BDP_FB, "fbclk", "mm_sel", 22), 77e9862118SShunli Wang GATE_BDP0(CLK_BDP_VDO_DRAM, "vdo_dram", "mm_sel", 23), 78e9862118SShunli Wang GATE_BDP0(CLK_BDP_VDO_2FS, "vdo_2fs", "di_sel", 24), 79e9862118SShunli Wang GATE_BDP0(CLK_BDP_VDO_B, "vdo_bclk", "mm_sel", 25), 80e9862118SShunli Wang GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26), 81e9862118SShunli Wang GATE_BDP0(CLK_BDP_WR_DI_DRAM, "wr_di_dram", "mm_sel", 27), 82e9862118SShunli Wang GATE_BDP0(CLK_BDP_WR_DI_B, "wr_di_bclk", "mm_sel", 28), 83e9862118SShunli Wang GATE_BDP0(CLK_BDP_NR_PXL, "nr_pxl", "nr_sel", 29), 84e9862118SShunli Wang GATE_BDP0(CLK_BDP_NR_DRAM, "nr_dram", "mm_sel", 30), 85e9862118SShunli Wang GATE_BDP0(CLK_BDP_NR_B, "nr_bclk", "mm_sel", 31), 86e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_F, "rx_fclk", "hadds2_fbclk", 0), 87e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_X, "rx_xclk", "clk26m", 1), 88e9862118SShunli Wang GATE_BDP1(CLK_BDP_RXPDT, "rxpdtclk", "hdmi_0_pix340m", 2), 89e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_CSCL_N, "rx_cscl_n", "clk26m", 3), 90e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_CSCL, "rx_cscl", "clk26m", 4), 91e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_DDCSCL_N, "rx_ddcscl_n", "hdmi_scl_rx", 5), 92e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_DDCSCL, "rx_ddcscl", "hdmi_scl_rx", 6), 93e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_VCO, "rx_vcoclk", "hadds2pll_294m", 7), 94e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_DP, "rx_dpclk", "hdmi_0_pll340m", 8), 95e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_P, "rx_pclk", "hdmi_0_pll340m", 9), 96e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_M, "rx_mclk", "hadds2pll_294m", 10), 97e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_PLL, "rx_pllclk", "hdmi_0_pix340m", 11), 98e9862118SShunli Wang GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12), 99e9862118SShunli Wang GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13), 100e9862118SShunli Wang GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14), 101e9862118SShunli Wang GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15), 102e9862118SShunli Wang GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16), 103e9862118SShunli Wang }; 104e9862118SShunli Wang 105e9862118SShunli Wang static const struct of_device_id of_match_clk_mt2701_bdp[] = { 106e9862118SShunli Wang { .compatible = "mediatek,mt2701-bdpsys", }, 107e9862118SShunli Wang {} 108e9862118SShunli Wang }; 109e9862118SShunli Wang 110e9862118SShunli Wang static int clk_mt2701_bdp_probe(struct platform_device *pdev) 111e9862118SShunli Wang { 112e9862118SShunli Wang struct clk_onecell_data *clk_data; 113e9862118SShunli Wang int r; 114e9862118SShunli Wang struct device_node *node = pdev->dev.of_node; 115e9862118SShunli Wang 116e9862118SShunli Wang clk_data = mtk_alloc_clk_data(CLK_BDP_NR); 117e9862118SShunli Wang 118e9862118SShunli Wang mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks), 119e9862118SShunli Wang clk_data); 120e9862118SShunli Wang 121e9862118SShunli Wang r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 122e9862118SShunli Wang if (r) 123e9862118SShunli Wang dev_err(&pdev->dev, 124e9862118SShunli Wang "could not register clock provider: %s: %d\n", 125e9862118SShunli Wang pdev->name, r); 126e9862118SShunli Wang 127e9862118SShunli Wang return r; 128e9862118SShunli Wang } 129e9862118SShunli Wang 130e9862118SShunli Wang static struct platform_driver clk_mt2701_bdp_drv = { 131e9862118SShunli Wang .probe = clk_mt2701_bdp_probe, 132e9862118SShunli Wang .driver = { 133e9862118SShunli Wang .name = "clk-mt2701-bdp", 134e9862118SShunli Wang .of_match_table = of_match_clk_mt2701_bdp, 135e9862118SShunli Wang }, 136e9862118SShunli Wang }; 137e9862118SShunli Wang 138e9862118SShunli Wang builtin_platform_driver(clk_mt2701_bdp_drv); 139