11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e9862118SShunli Wang /* 3e9862118SShunli Wang * Copyright (c) 2014 MediaTek Inc. 4e9862118SShunli Wang * Author: Shunli Wang <shunli.wang@mediatek.com> 5e9862118SShunli Wang */ 6e9862118SShunli Wang 7e9862118SShunli Wang #include <linux/clk-provider.h> 8e9862118SShunli Wang #include <linux/platform_device.h> 9e9862118SShunli Wang 10e9862118SShunli Wang #include "clk-mtk.h" 11e9862118SShunli Wang #include "clk-gate.h" 12e9862118SShunli Wang 13e9862118SShunli Wang #include <dt-bindings/clock/mt2701-clk.h> 14e9862118SShunli Wang 15e9862118SShunli Wang static const struct mtk_gate_regs bdp0_cg_regs = { 16e9862118SShunli Wang .set_ofs = 0x0104, 17e9862118SShunli Wang .clr_ofs = 0x0108, 18e9862118SShunli Wang .sta_ofs = 0x0100, 19e9862118SShunli Wang }; 20e9862118SShunli Wang 21e9862118SShunli Wang static const struct mtk_gate_regs bdp1_cg_regs = { 22e9862118SShunli Wang .set_ofs = 0x0114, 23e9862118SShunli Wang .clr_ofs = 0x0118, 24e9862118SShunli Wang .sta_ofs = 0x0110, 25e9862118SShunli Wang }; 26e9862118SShunli Wang 274c85e20bSAngeloGioacchino Del Regno #define GATE_BDP0(_id, _name, _parent, _shift) \ 284c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &bdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) 29e9862118SShunli Wang 304c85e20bSAngeloGioacchino Del Regno #define GATE_BDP1(_id, _name, _parent, _shift) \ 314c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &bdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) 32e9862118SShunli Wang 33e9862118SShunli Wang static const struct mtk_gate bdp_clks[] = { 34e9862118SShunli Wang GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0), 35e9862118SShunli Wang GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1), 36e9862118SShunli Wang GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2), 37e9862118SShunli Wang GATE_BDP0(CLK_BDP_WR_VDI_PXL, "wr_vdi_pxl", "hdmi_0_deep340m", 3), 38e9862118SShunli Wang GATE_BDP0(CLK_BDP_WR_VDI_DRAM, "wr_vdi_dram", "mm_sel", 4), 39e9862118SShunli Wang GATE_BDP0(CLK_BDP_WR_B, "wr_bclk", "mm_sel", 5), 40e9862118SShunli Wang GATE_BDP0(CLK_BDP_DGI_IN, "dgi_in", "dpi1_sel", 6), 41e9862118SShunli Wang GATE_BDP0(CLK_BDP_DGI_OUT, "dgi_out", "dpi1_sel", 7), 42e9862118SShunli Wang GATE_BDP0(CLK_BDP_FMT_MAST_27, "fmt_mast_27", "dpi1_sel", 8), 43e9862118SShunli Wang GATE_BDP0(CLK_BDP_FMT_B, "fmt_bclk", "mm_sel", 9), 44e9862118SShunli Wang GATE_BDP0(CLK_BDP_OSD_B, "osd_bclk", "mm_sel", 10), 45e9862118SShunli Wang GATE_BDP0(CLK_BDP_OSD_DRAM, "osd_dram", "mm_sel", 11), 46e9862118SShunli Wang GATE_BDP0(CLK_BDP_OSD_AGENT, "osd_agent", "osd_sel", 12), 47e9862118SShunli Wang GATE_BDP0(CLK_BDP_OSD_PXL, "osd_pxl", "dpi1_sel", 13), 48e9862118SShunli Wang GATE_BDP0(CLK_BDP_RLE_B, "rle_bclk", "mm_sel", 14), 49e9862118SShunli Wang GATE_BDP0(CLK_BDP_RLE_AGENT, "rle_agent", "mm_sel", 15), 50e9862118SShunli Wang GATE_BDP0(CLK_BDP_RLE_DRAM, "rle_dram", "mm_sel", 16), 51e9862118SShunli Wang GATE_BDP0(CLK_BDP_F27M, "f27m", "di_sel", 17), 52e9862118SShunli Wang GATE_BDP0(CLK_BDP_F27M_VDOUT, "f27m_vdout", "di_sel", 18), 53e9862118SShunli Wang GATE_BDP0(CLK_BDP_F27_74_74, "f27_74_74", "di_sel", 19), 54e9862118SShunli Wang GATE_BDP0(CLK_BDP_F2FS, "f2fs", "di_sel", 20), 55e9862118SShunli Wang GATE_BDP0(CLK_BDP_F2FS74_148, "f2fs74_148", "di_sel", 21), 56e9862118SShunli Wang GATE_BDP0(CLK_BDP_FB, "fbclk", "mm_sel", 22), 57e9862118SShunli Wang GATE_BDP0(CLK_BDP_VDO_DRAM, "vdo_dram", "mm_sel", 23), 58e9862118SShunli Wang GATE_BDP0(CLK_BDP_VDO_2FS, "vdo_2fs", "di_sel", 24), 59e9862118SShunli Wang GATE_BDP0(CLK_BDP_VDO_B, "vdo_bclk", "mm_sel", 25), 60e9862118SShunli Wang GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26), 61e9862118SShunli Wang GATE_BDP0(CLK_BDP_WR_DI_DRAM, "wr_di_dram", "mm_sel", 27), 62e9862118SShunli Wang GATE_BDP0(CLK_BDP_WR_DI_B, "wr_di_bclk", "mm_sel", 28), 63e9862118SShunli Wang GATE_BDP0(CLK_BDP_NR_PXL, "nr_pxl", "nr_sel", 29), 64e9862118SShunli Wang GATE_BDP0(CLK_BDP_NR_DRAM, "nr_dram", "mm_sel", 30), 65e9862118SShunli Wang GATE_BDP0(CLK_BDP_NR_B, "nr_bclk", "mm_sel", 31), 66e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_F, "rx_fclk", "hadds2_fbclk", 0), 67e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_X, "rx_xclk", "clk26m", 1), 68e9862118SShunli Wang GATE_BDP1(CLK_BDP_RXPDT, "rxpdtclk", "hdmi_0_pix340m", 2), 69e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_CSCL_N, "rx_cscl_n", "clk26m", 3), 70e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_CSCL, "rx_cscl", "clk26m", 4), 71e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_DDCSCL_N, "rx_ddcscl_n", "hdmi_scl_rx", 5), 72e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_DDCSCL, "rx_ddcscl", "hdmi_scl_rx", 6), 73e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_VCO, "rx_vcoclk", "hadds2pll_294m", 7), 74e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_DP, "rx_dpclk", "hdmi_0_pll340m", 8), 75e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_P, "rx_pclk", "hdmi_0_pll340m", 9), 76e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_M, "rx_mclk", "hadds2pll_294m", 10), 77e9862118SShunli Wang GATE_BDP1(CLK_BDP_RX_PLL, "rx_pllclk", "hdmi_0_pix340m", 11), 78e9862118SShunli Wang GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12), 79e9862118SShunli Wang GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13), 80e9862118SShunli Wang GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14), 81e9862118SShunli Wang GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15), 82e9862118SShunli Wang GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16), 83e9862118SShunli Wang }; 84e9862118SShunli Wang 85973d1607SMiles Chen static const struct mtk_clk_desc bdp_desc = { 86973d1607SMiles Chen .clks = bdp_clks, 87973d1607SMiles Chen .num_clks = ARRAY_SIZE(bdp_clks), 88e9862118SShunli Wang }; 89e9862118SShunli Wang 90973d1607SMiles Chen static const struct of_device_id of_match_clk_mt2701_bdp[] = { 91e9862118SShunli Wang { 92973d1607SMiles Chen .compatible = "mediatek,mt2701-bdpsys", 93973d1607SMiles Chen .data = &bdp_desc, 94973d1607SMiles Chen }, { 95973d1607SMiles Chen /* sentinel */ 96e9862118SShunli Wang } 97973d1607SMiles Chen }; 9865c9ad77SAngeloGioacchino Del Regno MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_bdp); 99e9862118SShunli Wang 100e9862118SShunli Wang static struct platform_driver clk_mt2701_bdp_drv = { 101973d1607SMiles Chen .probe = mtk_clk_simple_probe, 102*61ca6ee7SUwe Kleine-König .remove_new = mtk_clk_simple_remove, 103e9862118SShunli Wang .driver = { 104e9862118SShunli Wang .name = "clk-mt2701-bdp", 105e9862118SShunli Wang .of_match_table = of_match_clk_mt2701_bdp, 106e9862118SShunli Wang }, 107e9862118SShunli Wang }; 108164d240dSAngeloGioacchino Del Regno module_platform_driver(clk_mt2701_bdp_drv); 109a451da86SAngeloGioacchino Del Regno MODULE_LICENSE("GPL"); 110