1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: James Liao <jamesjj.liao@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 18 #include <linux/io.h> 19 #include <linux/slab.h> 20 #include <linux/delay.h> 21 #include <linux/clkdev.h> 22 23 #include "clk-mtk.h" 24 #include "clk-gate.h" 25 26 static int mtk_cg_bit_is_cleared(struct clk_hw *hw) 27 { 28 struct mtk_clk_gate *cg = to_clk_gate(hw); 29 u32 val; 30 31 regmap_read(cg->regmap, cg->sta_ofs, &val); 32 33 val &= BIT(cg->bit); 34 35 return val == 0; 36 } 37 38 static int mtk_cg_bit_is_set(struct clk_hw *hw) 39 { 40 struct mtk_clk_gate *cg = to_clk_gate(hw); 41 u32 val; 42 43 regmap_read(cg->regmap, cg->sta_ofs, &val); 44 45 val &= BIT(cg->bit); 46 47 return val != 0; 48 } 49 50 static void mtk_cg_set_bit(struct clk_hw *hw) 51 { 52 struct mtk_clk_gate *cg = to_clk_gate(hw); 53 54 regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit)); 55 } 56 57 static void mtk_cg_clr_bit(struct clk_hw *hw) 58 { 59 struct mtk_clk_gate *cg = to_clk_gate(hw); 60 61 regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit)); 62 } 63 64 static int mtk_cg_enable(struct clk_hw *hw) 65 { 66 mtk_cg_clr_bit(hw); 67 68 return 0; 69 } 70 71 static void mtk_cg_disable(struct clk_hw *hw) 72 { 73 mtk_cg_set_bit(hw); 74 } 75 76 static int mtk_cg_enable_inv(struct clk_hw *hw) 77 { 78 mtk_cg_set_bit(hw); 79 80 return 0; 81 } 82 83 static void mtk_cg_disable_inv(struct clk_hw *hw) 84 { 85 mtk_cg_clr_bit(hw); 86 } 87 88 const struct clk_ops mtk_clk_gate_ops_setclr = { 89 .is_enabled = mtk_cg_bit_is_cleared, 90 .enable = mtk_cg_enable, 91 .disable = mtk_cg_disable, 92 }; 93 94 const struct clk_ops mtk_clk_gate_ops_setclr_inv = { 95 .is_enabled = mtk_cg_bit_is_set, 96 .enable = mtk_cg_enable_inv, 97 .disable = mtk_cg_disable_inv, 98 }; 99 100 struct clk *mtk_clk_register_gate( 101 const char *name, 102 const char *parent_name, 103 struct regmap *regmap, 104 int set_ofs, 105 int clr_ofs, 106 int sta_ofs, 107 u8 bit, 108 const struct clk_ops *ops) 109 { 110 struct mtk_clk_gate *cg; 111 struct clk *clk; 112 struct clk_init_data init = {}; 113 114 cg = kzalloc(sizeof(*cg), GFP_KERNEL); 115 if (!cg) 116 return ERR_PTR(-ENOMEM); 117 118 init.name = name; 119 init.flags = CLK_SET_RATE_PARENT; 120 init.parent_names = parent_name ? &parent_name : NULL; 121 init.num_parents = parent_name ? 1 : 0; 122 init.ops = ops; 123 124 cg->regmap = regmap; 125 cg->set_ofs = set_ofs; 126 cg->clr_ofs = clr_ofs; 127 cg->sta_ofs = sta_ofs; 128 cg->bit = bit; 129 130 cg->hw.init = &init; 131 132 clk = clk_register(NULL, &cg->hw); 133 if (IS_ERR(clk)) 134 kfree(cg); 135 136 return clk; 137 } 138