1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: James Liao <jamesjj.liao@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 18 #include <linux/io.h> 19 #include <linux/slab.h> 20 #include <linux/delay.h> 21 #include <linux/clkdev.h> 22 23 #include "clk-mtk.h" 24 #include "clk-gate.h" 25 26 static int mtk_cg_bit_is_cleared(struct clk_hw *hw) 27 { 28 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); 29 u32 val; 30 31 regmap_read(cg->regmap, cg->sta_ofs, &val); 32 33 val &= BIT(cg->bit); 34 35 return val == 0; 36 } 37 38 static int mtk_cg_bit_is_set(struct clk_hw *hw) 39 { 40 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); 41 u32 val; 42 43 regmap_read(cg->regmap, cg->sta_ofs, &val); 44 45 val &= BIT(cg->bit); 46 47 return val != 0; 48 } 49 50 static void mtk_cg_set_bit(struct clk_hw *hw) 51 { 52 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); 53 54 regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit)); 55 } 56 57 static void mtk_cg_clr_bit(struct clk_hw *hw) 58 { 59 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); 60 61 regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit)); 62 } 63 64 static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw) 65 { 66 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); 67 u32 cgbit = BIT(cg->bit); 68 69 regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, cgbit); 70 } 71 72 static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw) 73 { 74 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); 75 u32 cgbit = BIT(cg->bit); 76 77 regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, 0); 78 } 79 80 static int mtk_cg_enable(struct clk_hw *hw) 81 { 82 mtk_cg_clr_bit(hw); 83 84 return 0; 85 } 86 87 static void mtk_cg_disable(struct clk_hw *hw) 88 { 89 mtk_cg_set_bit(hw); 90 } 91 92 static int mtk_cg_enable_inv(struct clk_hw *hw) 93 { 94 mtk_cg_set_bit(hw); 95 96 return 0; 97 } 98 99 static void mtk_cg_disable_inv(struct clk_hw *hw) 100 { 101 mtk_cg_clr_bit(hw); 102 } 103 104 static int mtk_cg_enable_no_setclr(struct clk_hw *hw) 105 { 106 mtk_cg_clr_bit_no_setclr(hw); 107 108 return 0; 109 } 110 111 static void mtk_cg_disable_no_setclr(struct clk_hw *hw) 112 { 113 mtk_cg_set_bit_no_setclr(hw); 114 } 115 116 static int mtk_cg_enable_inv_no_setclr(struct clk_hw *hw) 117 { 118 mtk_cg_set_bit_no_setclr(hw); 119 120 return 0; 121 } 122 123 static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw) 124 { 125 mtk_cg_clr_bit_no_setclr(hw); 126 } 127 128 const struct clk_ops mtk_clk_gate_ops_setclr = { 129 .is_enabled = mtk_cg_bit_is_cleared, 130 .enable = mtk_cg_enable, 131 .disable = mtk_cg_disable, 132 }; 133 134 const struct clk_ops mtk_clk_gate_ops_setclr_inv = { 135 .is_enabled = mtk_cg_bit_is_set, 136 .enable = mtk_cg_enable_inv, 137 .disable = mtk_cg_disable_inv, 138 }; 139 140 const struct clk_ops mtk_clk_gate_ops_no_setclr = { 141 .is_enabled = mtk_cg_bit_is_cleared, 142 .enable = mtk_cg_enable_no_setclr, 143 .disable = mtk_cg_disable_no_setclr, 144 }; 145 146 const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = { 147 .is_enabled = mtk_cg_bit_is_set, 148 .enable = mtk_cg_enable_inv_no_setclr, 149 .disable = mtk_cg_disable_inv_no_setclr, 150 }; 151 152 struct clk *mtk_clk_register_gate( 153 const char *name, 154 const char *parent_name, 155 struct regmap *regmap, 156 int set_ofs, 157 int clr_ofs, 158 int sta_ofs, 159 u8 bit, 160 const struct clk_ops *ops, 161 unsigned long flags) 162 { 163 struct mtk_clk_gate *cg; 164 struct clk *clk; 165 struct clk_init_data init = {}; 166 167 cg = kzalloc(sizeof(*cg), GFP_KERNEL); 168 if (!cg) 169 return ERR_PTR(-ENOMEM); 170 171 init.name = name; 172 init.flags = CLK_SET_RATE_PARENT; 173 init.parent_names = parent_name ? &parent_name : NULL; 174 init.num_parents = parent_name ? 1 : 0; 175 init.ops = ops; 176 init.flags = flags; 177 178 cg->regmap = regmap; 179 cg->set_ofs = set_ofs; 180 cg->clr_ofs = clr_ofs; 181 cg->sta_ofs = sta_ofs; 182 cg->bit = bit; 183 184 cg->hw.init = &init; 185 186 clk = clk_register(NULL, &cg->hw); 187 if (IS_ERR(clk)) 188 kfree(cg); 189 190 return clk; 191 } 192