1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/mfd/syscon.h> 9 #include <linux/module.h> 10 #include <linux/printk.h> 11 #include <linux/regmap.h> 12 #include <linux/slab.h> 13 #include <linux/types.h> 14 15 #include "clk-gate.h" 16 17 struct mtk_clk_gate { 18 struct clk_hw hw; 19 struct regmap *regmap; 20 int set_ofs; 21 int clr_ofs; 22 int sta_ofs; 23 u8 bit; 24 }; 25 26 static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw) 27 { 28 return container_of(hw, struct mtk_clk_gate, hw); 29 } 30 31 static u32 mtk_get_clockgating(struct clk_hw *hw) 32 { 33 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); 34 u32 val; 35 36 regmap_read(cg->regmap, cg->sta_ofs, &val); 37 38 return val & BIT(cg->bit); 39 } 40 41 static int mtk_cg_bit_is_cleared(struct clk_hw *hw) 42 { 43 return mtk_get_clockgating(hw) == 0; 44 } 45 46 static int mtk_cg_bit_is_set(struct clk_hw *hw) 47 { 48 return mtk_get_clockgating(hw) != 0; 49 } 50 51 static void mtk_cg_set_bit(struct clk_hw *hw) 52 { 53 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); 54 55 regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit)); 56 } 57 58 static void mtk_cg_clr_bit(struct clk_hw *hw) 59 { 60 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); 61 62 regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit)); 63 } 64 65 static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw) 66 { 67 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); 68 69 regmap_set_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit)); 70 } 71 72 static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw) 73 { 74 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); 75 76 regmap_clear_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit)); 77 } 78 79 static int mtk_cg_enable(struct clk_hw *hw) 80 { 81 mtk_cg_clr_bit(hw); 82 83 return 0; 84 } 85 86 static void mtk_cg_disable(struct clk_hw *hw) 87 { 88 mtk_cg_set_bit(hw); 89 } 90 91 static int mtk_cg_enable_inv(struct clk_hw *hw) 92 { 93 mtk_cg_set_bit(hw); 94 95 return 0; 96 } 97 98 static void mtk_cg_disable_inv(struct clk_hw *hw) 99 { 100 mtk_cg_clr_bit(hw); 101 } 102 103 static int mtk_cg_enable_no_setclr(struct clk_hw *hw) 104 { 105 mtk_cg_clr_bit_no_setclr(hw); 106 107 return 0; 108 } 109 110 static void mtk_cg_disable_no_setclr(struct clk_hw *hw) 111 { 112 mtk_cg_set_bit_no_setclr(hw); 113 } 114 115 static int mtk_cg_enable_inv_no_setclr(struct clk_hw *hw) 116 { 117 mtk_cg_set_bit_no_setclr(hw); 118 119 return 0; 120 } 121 122 static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw) 123 { 124 mtk_cg_clr_bit_no_setclr(hw); 125 } 126 127 const struct clk_ops mtk_clk_gate_ops_setclr = { 128 .is_enabled = mtk_cg_bit_is_cleared, 129 .enable = mtk_cg_enable, 130 .disable = mtk_cg_disable, 131 }; 132 EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr); 133 134 const struct clk_ops mtk_clk_gate_ops_setclr_inv = { 135 .is_enabled = mtk_cg_bit_is_set, 136 .enable = mtk_cg_enable_inv, 137 .disable = mtk_cg_disable_inv, 138 }; 139 EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_inv); 140 141 const struct clk_ops mtk_clk_gate_ops_no_setclr = { 142 .is_enabled = mtk_cg_bit_is_cleared, 143 .enable = mtk_cg_enable_no_setclr, 144 .disable = mtk_cg_disable_no_setclr, 145 }; 146 EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr); 147 148 const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = { 149 .is_enabled = mtk_cg_bit_is_set, 150 .enable = mtk_cg_enable_inv_no_setclr, 151 .disable = mtk_cg_disable_inv_no_setclr, 152 }; 153 EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv); 154 155 static struct clk_hw *mtk_clk_register_gate(const char *name, 156 const char *parent_name, 157 struct regmap *regmap, int set_ofs, 158 int clr_ofs, int sta_ofs, u8 bit, 159 const struct clk_ops *ops, 160 unsigned long flags, struct device *dev) 161 { 162 struct mtk_clk_gate *cg; 163 int ret; 164 struct clk_init_data init = {}; 165 166 cg = kzalloc(sizeof(*cg), GFP_KERNEL); 167 if (!cg) 168 return ERR_PTR(-ENOMEM); 169 170 init.name = name; 171 init.flags = flags | CLK_SET_RATE_PARENT; 172 init.parent_names = parent_name ? &parent_name : NULL; 173 init.num_parents = parent_name ? 1 : 0; 174 init.ops = ops; 175 176 cg->regmap = regmap; 177 cg->set_ofs = set_ofs; 178 cg->clr_ofs = clr_ofs; 179 cg->sta_ofs = sta_ofs; 180 cg->bit = bit; 181 182 cg->hw.init = &init; 183 184 ret = clk_hw_register(dev, &cg->hw); 185 if (ret) { 186 kfree(cg); 187 return ERR_PTR(ret); 188 } 189 190 return &cg->hw; 191 } 192 193 static void mtk_clk_unregister_gate(struct clk_hw *hw) 194 { 195 struct mtk_clk_gate *cg; 196 if (!hw) 197 return; 198 199 cg = to_mtk_clk_gate(hw); 200 201 clk_hw_unregister(hw); 202 kfree(cg); 203 } 204 205 int mtk_clk_register_gates_with_dev(struct device_node *node, 206 const struct mtk_gate *clks, int num, 207 struct clk_hw_onecell_data *clk_data, 208 struct device *dev) 209 { 210 int i; 211 struct clk_hw *hw; 212 struct regmap *regmap; 213 214 if (!clk_data) 215 return -ENOMEM; 216 217 regmap = device_node_to_regmap(node); 218 if (IS_ERR(regmap)) { 219 pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap); 220 return PTR_ERR(regmap); 221 } 222 223 for (i = 0; i < num; i++) { 224 const struct mtk_gate *gate = &clks[i]; 225 226 if (!IS_ERR_OR_NULL(clk_data->hws[gate->id])) { 227 pr_warn("%pOF: Trying to register duplicate clock ID: %d\n", 228 node, gate->id); 229 continue; 230 } 231 232 hw = mtk_clk_register_gate(gate->name, gate->parent_name, 233 regmap, 234 gate->regs->set_ofs, 235 gate->regs->clr_ofs, 236 gate->regs->sta_ofs, 237 gate->shift, gate->ops, 238 gate->flags, dev); 239 240 if (IS_ERR(hw)) { 241 pr_err("Failed to register clk %s: %pe\n", gate->name, 242 hw); 243 goto err; 244 } 245 246 clk_data->hws[gate->id] = hw; 247 } 248 249 return 0; 250 251 err: 252 while (--i >= 0) { 253 const struct mtk_gate *gate = &clks[i]; 254 255 if (IS_ERR_OR_NULL(clk_data->hws[gate->id])) 256 continue; 257 258 mtk_clk_unregister_gate(clk_data->hws[gate->id]); 259 clk_data->hws[gate->id] = ERR_PTR(-ENOENT); 260 } 261 262 return PTR_ERR(hw); 263 } 264 265 int mtk_clk_register_gates(struct device_node *node, 266 const struct mtk_gate *clks, int num, 267 struct clk_hw_onecell_data *clk_data) 268 { 269 return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL); 270 } 271 EXPORT_SYMBOL_GPL(mtk_clk_register_gates); 272 273 void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, 274 struct clk_hw_onecell_data *clk_data) 275 { 276 int i; 277 278 if (!clk_data) 279 return; 280 281 for (i = num; i > 0; i--) { 282 const struct mtk_gate *gate = &clks[i - 1]; 283 284 if (IS_ERR_OR_NULL(clk_data->hws[gate->id])) 285 continue; 286 287 mtk_clk_unregister_gate(clk_data->hws[gate->id]); 288 clk_data->hws[gate->id] = ERR_PTR(-ENOENT); 289 } 290 } 291 EXPORT_SYMBOL_GPL(mtk_clk_unregister_gates); 292 293 MODULE_LICENSE("GPL"); 294