xref: /openbmc/linux/drivers/clk/mediatek/clk-gate.c (revision 1e70d57e) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014 MediaTek Inc.
4  * Author: James Liao <jamesjj.liao@mediatek.com>
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/mfd/syscon.h>
9 #include <linux/module.h>
10 #include <linux/printk.h>
11 #include <linux/regmap.h>
12 #include <linux/slab.h>
13 #include <linux/types.h>
14 
15 #include "clk-gate.h"
16 
17 struct mtk_clk_gate {
18 	struct clk_hw	hw;
19 	struct regmap	*regmap;
20 	int		set_ofs;
21 	int		clr_ofs;
22 	int		sta_ofs;
23 	u8		bit;
24 };
25 
26 static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
27 {
28 	return container_of(hw, struct mtk_clk_gate, hw);
29 }
30 
31 static u32 mtk_get_clockgating(struct clk_hw *hw)
32 {
33 	struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
34 	u32 val;
35 
36 	regmap_read(cg->regmap, cg->sta_ofs, &val);
37 
38 	return val & BIT(cg->bit);
39 }
40 
41 static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
42 {
43 	return mtk_get_clockgating(hw) == 0;
44 }
45 
46 static int mtk_cg_bit_is_set(struct clk_hw *hw)
47 {
48 	return mtk_get_clockgating(hw) != 0;
49 }
50 
51 static void mtk_cg_set_bit(struct clk_hw *hw)
52 {
53 	struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
54 
55 	regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
56 }
57 
58 static void mtk_cg_clr_bit(struct clk_hw *hw)
59 {
60 	struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
61 
62 	regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
63 }
64 
65 static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
66 {
67 	struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
68 
69 	regmap_set_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
70 }
71 
72 static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
73 {
74 	struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
75 
76 	regmap_clear_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
77 }
78 
79 static int mtk_cg_enable(struct clk_hw *hw)
80 {
81 	mtk_cg_clr_bit(hw);
82 
83 	return 0;
84 }
85 
86 static void mtk_cg_disable(struct clk_hw *hw)
87 {
88 	mtk_cg_set_bit(hw);
89 }
90 
91 static int mtk_cg_enable_inv(struct clk_hw *hw)
92 {
93 	mtk_cg_set_bit(hw);
94 
95 	return 0;
96 }
97 
98 static void mtk_cg_disable_inv(struct clk_hw *hw)
99 {
100 	mtk_cg_clr_bit(hw);
101 }
102 
103 static int mtk_cg_enable_no_setclr(struct clk_hw *hw)
104 {
105 	mtk_cg_clr_bit_no_setclr(hw);
106 
107 	return 0;
108 }
109 
110 static void mtk_cg_disable_no_setclr(struct clk_hw *hw)
111 {
112 	mtk_cg_set_bit_no_setclr(hw);
113 }
114 
115 static int mtk_cg_enable_inv_no_setclr(struct clk_hw *hw)
116 {
117 	mtk_cg_set_bit_no_setclr(hw);
118 
119 	return 0;
120 }
121 
122 static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw)
123 {
124 	mtk_cg_clr_bit_no_setclr(hw);
125 }
126 
127 const struct clk_ops mtk_clk_gate_ops_setclr = {
128 	.is_enabled	= mtk_cg_bit_is_cleared,
129 	.enable		= mtk_cg_enable,
130 	.disable	= mtk_cg_disable,
131 };
132 EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr);
133 
134 const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
135 	.is_enabled	= mtk_cg_bit_is_set,
136 	.enable		= mtk_cg_enable_inv,
137 	.disable	= mtk_cg_disable_inv,
138 };
139 EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_inv);
140 
141 const struct clk_ops mtk_clk_gate_ops_no_setclr = {
142 	.is_enabled	= mtk_cg_bit_is_cleared,
143 	.enable		= mtk_cg_enable_no_setclr,
144 	.disable	= mtk_cg_disable_no_setclr,
145 };
146 EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr);
147 
148 const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
149 	.is_enabled	= mtk_cg_bit_is_set,
150 	.enable		= mtk_cg_enable_inv_no_setclr,
151 	.disable	= mtk_cg_disable_inv_no_setclr,
152 };
153 EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
154 
155 static struct clk *mtk_clk_register_gate(const char *name,
156 					 const char *parent_name,
157 					 struct regmap *regmap, int set_ofs,
158 					 int clr_ofs, int sta_ofs, u8 bit,
159 					 const struct clk_ops *ops,
160 					 unsigned long flags, struct device *dev)
161 {
162 	struct mtk_clk_gate *cg;
163 	struct clk *clk;
164 	struct clk_init_data init = {};
165 
166 	cg = kzalloc(sizeof(*cg), GFP_KERNEL);
167 	if (!cg)
168 		return ERR_PTR(-ENOMEM);
169 
170 	init.name = name;
171 	init.flags = flags | CLK_SET_RATE_PARENT;
172 	init.parent_names = parent_name ? &parent_name : NULL;
173 	init.num_parents = parent_name ? 1 : 0;
174 	init.ops = ops;
175 
176 	cg->regmap = regmap;
177 	cg->set_ofs = set_ofs;
178 	cg->clr_ofs = clr_ofs;
179 	cg->sta_ofs = sta_ofs;
180 	cg->bit = bit;
181 
182 	cg->hw.init = &init;
183 
184 	clk = clk_register(dev, &cg->hw);
185 	if (IS_ERR(clk))
186 		kfree(cg);
187 
188 	return clk;
189 }
190 
191 static void mtk_clk_unregister_gate(struct clk *clk)
192 {
193 	struct mtk_clk_gate *cg;
194 	struct clk_hw *hw;
195 
196 	hw = __clk_get_hw(clk);
197 	if (!hw)
198 		return;
199 
200 	cg = to_mtk_clk_gate(hw);
201 
202 	clk_unregister(clk);
203 	kfree(cg);
204 }
205 
206 int mtk_clk_register_gates_with_dev(struct device_node *node,
207 				    const struct mtk_gate *clks, int num,
208 				    struct clk_onecell_data *clk_data,
209 				    struct device *dev)
210 {
211 	int i;
212 	struct clk *clk;
213 	struct regmap *regmap;
214 
215 	if (!clk_data)
216 		return -ENOMEM;
217 
218 	regmap = device_node_to_regmap(node);
219 	if (IS_ERR(regmap)) {
220 		pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap);
221 		return PTR_ERR(regmap);
222 	}
223 
224 	for (i = 0; i < num; i++) {
225 		const struct mtk_gate *gate = &clks[i];
226 
227 		if (!IS_ERR_OR_NULL(clk_data->clks[gate->id])) {
228 			pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
229 				node, gate->id);
230 			continue;
231 		}
232 
233 		clk = mtk_clk_register_gate(gate->name, gate->parent_name,
234 					    regmap,
235 					    gate->regs->set_ofs,
236 					    gate->regs->clr_ofs,
237 					    gate->regs->sta_ofs,
238 					    gate->shift, gate->ops,
239 					    gate->flags, dev);
240 
241 		if (IS_ERR(clk)) {
242 			pr_err("Failed to register clk %s: %pe\n", gate->name, clk);
243 			goto err;
244 		}
245 
246 		clk_data->clks[gate->id] = clk;
247 	}
248 
249 	return 0;
250 
251 err:
252 	while (--i >= 0) {
253 		const struct mtk_gate *gate = &clks[i];
254 
255 		if (IS_ERR_OR_NULL(clk_data->clks[gate->id]))
256 			continue;
257 
258 		mtk_clk_unregister_gate(clk_data->clks[gate->id]);
259 		clk_data->clks[gate->id] = ERR_PTR(-ENOENT);
260 	}
261 
262 	return PTR_ERR(clk);
263 }
264 
265 int mtk_clk_register_gates(struct device_node *node,
266 			   const struct mtk_gate *clks, int num,
267 			   struct clk_onecell_data *clk_data)
268 {
269 	return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL);
270 }
271 EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
272 
273 void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
274 			      struct clk_onecell_data *clk_data)
275 {
276 	int i;
277 
278 	if (!clk_data)
279 		return;
280 
281 	for (i = num; i > 0; i--) {
282 		const struct mtk_gate *gate = &clks[i - 1];
283 
284 		if (IS_ERR_OR_NULL(clk_data->clks[gate->id]))
285 			continue;
286 
287 		mtk_clk_unregister_gate(clk_data->clks[gate->id]);
288 		clk_data->clks[gate->id] = ERR_PTR(-ENOENT);
289 	}
290 }
291 EXPORT_SYMBOL_GPL(mtk_clk_unregister_gates);
292 
293 MODULE_LICENSE("GPL");
294