1 /* 2 * Ingenic JZ4780 SoC CGU driver 3 * 4 * Copyright (c) 2013-2015 Imagination Technologies 5 * Author: Paul Burton <paul.burton@mips.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/clk-provider.h> 19 #include <linux/delay.h> 20 #include <linux/io.h> 21 #include <linux/of.h> 22 #include <dt-bindings/clock/jz4780-cgu.h> 23 #include "cgu.h" 24 25 /* CGU register offsets */ 26 #define CGU_REG_CLOCKCONTROL 0x00 27 #define CGU_REG_PLLCONTROL 0x0c 28 #define CGU_REG_APLL 0x10 29 #define CGU_REG_MPLL 0x14 30 #define CGU_REG_EPLL 0x18 31 #define CGU_REG_VPLL 0x1c 32 #define CGU_REG_CLKGR0 0x20 33 #define CGU_REG_OPCR 0x24 34 #define CGU_REG_CLKGR1 0x28 35 #define CGU_REG_DDRCDR 0x2c 36 #define CGU_REG_VPUCDR 0x30 37 #define CGU_REG_USBPCR 0x3c 38 #define CGU_REG_USBRDT 0x40 39 #define CGU_REG_USBVBFIL 0x44 40 #define CGU_REG_USBPCR1 0x48 41 #define CGU_REG_LP0CDR 0x54 42 #define CGU_REG_I2SCDR 0x60 43 #define CGU_REG_LP1CDR 0x64 44 #define CGU_REG_MSC0CDR 0x68 45 #define CGU_REG_UHCCDR 0x6c 46 #define CGU_REG_SSICDR 0x74 47 #define CGU_REG_CIMCDR 0x7c 48 #define CGU_REG_PCMCDR 0x84 49 #define CGU_REG_GPUCDR 0x88 50 #define CGU_REG_HDMICDR 0x8c 51 #define CGU_REG_MSC1CDR 0xa4 52 #define CGU_REG_MSC2CDR 0xa8 53 #define CGU_REG_BCHCDR 0xac 54 #define CGU_REG_CLOCKSTATUS 0xd4 55 56 /* bits within the OPCR register */ 57 #define OPCR_SPENDN0 (1 << 7) 58 #define OPCR_SPENDN1 (1 << 6) 59 60 /* bits within the USBPCR register */ 61 #define USBPCR_USB_MODE BIT(31) 62 #define USBPCR_IDPULLUP_MASK (0x3 << 28) 63 #define USBPCR_COMMONONN BIT(25) 64 #define USBPCR_VBUSVLDEXT BIT(24) 65 #define USBPCR_VBUSVLDEXTSEL BIT(23) 66 #define USBPCR_POR BIT(22) 67 #define USBPCR_OTG_DISABLE BIT(20) 68 #define USBPCR_COMPDISTUNE_MASK (0x7 << 17) 69 #define USBPCR_OTGTUNE_MASK (0x7 << 14) 70 #define USBPCR_SQRXTUNE_MASK (0x7 << 11) 71 #define USBPCR_TXFSLSTUNE_MASK (0xf << 7) 72 #define USBPCR_TXPREEMPHTUNE BIT(6) 73 #define USBPCR_TXHSXVTUNE_MASK (0x3 << 4) 74 #define USBPCR_TXVREFTUNE_MASK 0xf 75 76 /* bits within the USBPCR1 register */ 77 #define USBPCR1_REFCLKSEL_SHIFT 26 78 #define USBPCR1_REFCLKSEL_MASK (0x3 << USBPCR1_REFCLKSEL_SHIFT) 79 #define USBPCR1_REFCLKSEL_CORE (0x2 << USBPCR1_REFCLKSEL_SHIFT) 80 #define USBPCR1_REFCLKDIV_SHIFT 24 81 #define USBPCR1_REFCLKDIV_MASK (0x3 << USBPCR1_REFCLKDIV_SHIFT) 82 #define USBPCR1_REFCLKDIV_19_2 (0x3 << USBPCR1_REFCLKDIV_SHIFT) 83 #define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT) 84 #define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT) 85 #define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT) 86 #define USBPCR1_USB_SEL BIT(28) 87 #define USBPCR1_WORD_IF0 BIT(19) 88 #define USBPCR1_WORD_IF1 BIT(18) 89 90 /* bits within the USBRDT register */ 91 #define USBRDT_VBFIL_LD_EN BIT(25) 92 #define USBRDT_USBRDT_MASK 0x7fffff 93 94 /* bits within the USBVBFIL register */ 95 #define USBVBFIL_IDDIGFIL_SHIFT 16 96 #define USBVBFIL_IDDIGFIL_MASK (0xffff << USBVBFIL_IDDIGFIL_SHIFT) 97 #define USBVBFIL_USBVBFIL_MASK (0xffff) 98 99 static struct ingenic_cgu *cgu; 100 101 static u8 jz4780_otg_phy_get_parent(struct clk_hw *hw) 102 { 103 /* we only use CLKCORE, revisit if that ever changes */ 104 return 0; 105 } 106 107 static int jz4780_otg_phy_set_parent(struct clk_hw *hw, u8 idx) 108 { 109 unsigned long flags; 110 u32 usbpcr1; 111 112 if (idx > 0) 113 return -EINVAL; 114 115 spin_lock_irqsave(&cgu->lock, flags); 116 117 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); 118 usbpcr1 &= ~USBPCR1_REFCLKSEL_MASK; 119 /* we only use CLKCORE */ 120 usbpcr1 |= USBPCR1_REFCLKSEL_CORE; 121 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); 122 123 spin_unlock_irqrestore(&cgu->lock, flags); 124 return 0; 125 } 126 127 static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw, 128 unsigned long parent_rate) 129 { 130 u32 usbpcr1; 131 unsigned refclk_div; 132 133 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); 134 refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK; 135 136 switch (refclk_div) { 137 case USBPCR1_REFCLKDIV_12: 138 return 12000000; 139 140 case USBPCR1_REFCLKDIV_24: 141 return 24000000; 142 143 case USBPCR1_REFCLKDIV_48: 144 return 48000000; 145 146 case USBPCR1_REFCLKDIV_19_2: 147 return 19200000; 148 } 149 150 BUG(); 151 return parent_rate; 152 } 153 154 static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate, 155 unsigned long *parent_rate) 156 { 157 if (req_rate < 15600000) 158 return 12000000; 159 160 if (req_rate < 21600000) 161 return 19200000; 162 163 if (req_rate < 36000000) 164 return 24000000; 165 166 return 48000000; 167 } 168 169 static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate, 170 unsigned long parent_rate) 171 { 172 unsigned long flags; 173 u32 usbpcr1, div_bits; 174 175 switch (req_rate) { 176 case 12000000: 177 div_bits = USBPCR1_REFCLKDIV_12; 178 break; 179 180 case 19200000: 181 div_bits = USBPCR1_REFCLKDIV_19_2; 182 break; 183 184 case 24000000: 185 div_bits = USBPCR1_REFCLKDIV_24; 186 break; 187 188 case 48000000: 189 div_bits = USBPCR1_REFCLKDIV_48; 190 break; 191 192 default: 193 return -EINVAL; 194 } 195 196 spin_lock_irqsave(&cgu->lock, flags); 197 198 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); 199 usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK; 200 usbpcr1 |= div_bits; 201 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); 202 203 spin_unlock_irqrestore(&cgu->lock, flags); 204 return 0; 205 } 206 207 static const struct clk_ops jz4780_otg_phy_ops = { 208 .get_parent = jz4780_otg_phy_get_parent, 209 .set_parent = jz4780_otg_phy_set_parent, 210 211 .recalc_rate = jz4780_otg_phy_recalc_rate, 212 .round_rate = jz4780_otg_phy_round_rate, 213 .set_rate = jz4780_otg_phy_set_rate, 214 }; 215 216 static const s8 pll_od_encoding[16] = { 217 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 218 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 219 }; 220 221 static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { 222 223 /* External clocks */ 224 225 [JZ4780_CLK_EXCLK] = { "ext", CGU_CLK_EXT }, 226 [JZ4780_CLK_RTCLK] = { "rtc", CGU_CLK_EXT }, 227 228 /* PLLs */ 229 230 #define DEF_PLL(name) { \ 231 .reg = CGU_REG_ ## name, \ 232 .m_shift = 19, \ 233 .m_bits = 13, \ 234 .m_offset = 1, \ 235 .n_shift = 13, \ 236 .n_bits = 6, \ 237 .n_offset = 1, \ 238 .od_shift = 9, \ 239 .od_bits = 4, \ 240 .od_max = 16, \ 241 .od_encoding = pll_od_encoding, \ 242 .stable_bit = 6, \ 243 .bypass_bit = 1, \ 244 .enable_bit = 0, \ 245 } 246 247 [JZ4780_CLK_APLL] = { 248 "apll", CGU_CLK_PLL, 249 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 250 .pll = DEF_PLL(APLL), 251 }, 252 253 [JZ4780_CLK_MPLL] = { 254 "mpll", CGU_CLK_PLL, 255 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 256 .pll = DEF_PLL(MPLL), 257 }, 258 259 [JZ4780_CLK_EPLL] = { 260 "epll", CGU_CLK_PLL, 261 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 262 .pll = DEF_PLL(EPLL), 263 }, 264 265 [JZ4780_CLK_VPLL] = { 266 "vpll", CGU_CLK_PLL, 267 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 268 .pll = DEF_PLL(VPLL), 269 }, 270 271 #undef DEF_PLL 272 273 /* Custom (SoC-specific) OTG PHY */ 274 275 [JZ4780_CLK_OTGPHY] = { 276 "otg_phy", CGU_CLK_CUSTOM, 277 .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 }, 278 .custom = { &jz4780_otg_phy_ops }, 279 }, 280 281 /* Muxes & dividers */ 282 283 [JZ4780_CLK_SCLKA] = { 284 "sclk_a", CGU_CLK_MUX, 285 .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK, 286 JZ4780_CLK_RTCLK }, 287 .mux = { CGU_REG_CLOCKCONTROL, 30, 2 }, 288 }, 289 290 [JZ4780_CLK_CPUMUX] = { 291 "cpumux", CGU_CLK_MUX, 292 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 293 JZ4780_CLK_EPLL }, 294 .mux = { CGU_REG_CLOCKCONTROL, 28, 2 }, 295 }, 296 297 [JZ4780_CLK_CPU] = { 298 "cpu", CGU_CLK_DIV, 299 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, 300 .div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 }, 301 }, 302 303 [JZ4780_CLK_L2CACHE] = { 304 "l2cache", CGU_CLK_DIV, 305 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, 306 .div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 }, 307 }, 308 309 [JZ4780_CLK_AHB0] = { 310 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV, 311 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 312 JZ4780_CLK_EPLL }, 313 .mux = { CGU_REG_CLOCKCONTROL, 26, 2 }, 314 .div = { CGU_REG_CLOCKCONTROL, 8, 1, 4, 21, -1, -1 }, 315 }, 316 317 [JZ4780_CLK_AHB2PMUX] = { 318 "ahb2_apb_mux", CGU_CLK_MUX, 319 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 320 JZ4780_CLK_RTCLK }, 321 .mux = { CGU_REG_CLOCKCONTROL, 24, 2 }, 322 }, 323 324 [JZ4780_CLK_AHB2] = { 325 "ahb2", CGU_CLK_DIV, 326 .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, 327 .div = { CGU_REG_CLOCKCONTROL, 12, 1, 4, 20, -1, -1 }, 328 }, 329 330 [JZ4780_CLK_PCLK] = { 331 "pclk", CGU_CLK_DIV, 332 .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, 333 .div = { CGU_REG_CLOCKCONTROL, 16, 1, 4, 20, -1, -1 }, 334 }, 335 336 [JZ4780_CLK_DDR] = { 337 "ddr", CGU_CLK_MUX | CGU_CLK_DIV, 338 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 }, 339 .mux = { CGU_REG_DDRCDR, 30, 2 }, 340 .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, 341 }, 342 343 [JZ4780_CLK_VPU] = { 344 "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, 345 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 346 JZ4780_CLK_EPLL, -1 }, 347 .mux = { CGU_REG_VPUCDR, 30, 2 }, 348 .div = { CGU_REG_VPUCDR, 0, 1, 4, 29, 28, 27 }, 349 .gate = { CGU_REG_CLKGR1, 2 }, 350 }, 351 352 [JZ4780_CLK_I2SPLL] = { 353 "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV, 354 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 }, 355 .mux = { CGU_REG_I2SCDR, 30, 1 }, 356 .div = { CGU_REG_I2SCDR, 0, 1, 8, 29, 28, 27 }, 357 }, 358 359 [JZ4780_CLK_I2S] = { 360 "i2s", CGU_CLK_MUX, 361 .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -1 }, 362 .mux = { CGU_REG_I2SCDR, 31, 1 }, 363 }, 364 365 [JZ4780_CLK_LCD0PIXCLK] = { 366 "lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV, 367 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 368 JZ4780_CLK_VPLL, -1 }, 369 .mux = { CGU_REG_LP0CDR, 30, 2 }, 370 .div = { CGU_REG_LP0CDR, 0, 1, 8, 28, 27, 26 }, 371 }, 372 373 [JZ4780_CLK_LCD1PIXCLK] = { 374 "lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV, 375 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 376 JZ4780_CLK_VPLL, -1 }, 377 .mux = { CGU_REG_LP1CDR, 30, 2 }, 378 .div = { CGU_REG_LP1CDR, 0, 1, 8, 28, 27, 26 }, 379 }, 380 381 [JZ4780_CLK_MSCMUX] = { 382 "msc_mux", CGU_CLK_MUX, 383 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 }, 384 .mux = { CGU_REG_MSC0CDR, 30, 2 }, 385 }, 386 387 [JZ4780_CLK_MSC0] = { 388 "msc0", CGU_CLK_DIV | CGU_CLK_GATE, 389 .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, 390 .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, 391 .gate = { CGU_REG_CLKGR0, 3 }, 392 }, 393 394 [JZ4780_CLK_MSC1] = { 395 "msc1", CGU_CLK_DIV | CGU_CLK_GATE, 396 .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, 397 .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, 398 .gate = { CGU_REG_CLKGR0, 11 }, 399 }, 400 401 [JZ4780_CLK_MSC2] = { 402 "msc2", CGU_CLK_DIV | CGU_CLK_GATE, 403 .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, 404 .div = { CGU_REG_MSC2CDR, 0, 2, 8, 29, 28, 27 }, 405 .gate = { CGU_REG_CLKGR0, 12 }, 406 }, 407 408 [JZ4780_CLK_UHC] = { 409 "uhc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, 410 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 411 JZ4780_CLK_EPLL, JZ4780_CLK_OTGPHY }, 412 .mux = { CGU_REG_UHCCDR, 30, 2 }, 413 .div = { CGU_REG_UHCCDR, 0, 1, 8, 29, 28, 27 }, 414 .gate = { CGU_REG_CLKGR0, 24 }, 415 }, 416 417 [JZ4780_CLK_SSIPLL] = { 418 "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, 419 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 }, 420 .mux = { CGU_REG_SSICDR, 30, 1 }, 421 .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 }, 422 }, 423 424 [JZ4780_CLK_SSI] = { 425 "ssi", CGU_CLK_MUX, 426 .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -1 }, 427 .mux = { CGU_REG_SSICDR, 31, 1 }, 428 }, 429 430 [JZ4780_CLK_CIMMCLK] = { 431 "cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV, 432 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 }, 433 .mux = { CGU_REG_CIMCDR, 31, 1 }, 434 .div = { CGU_REG_CIMCDR, 0, 1, 8, 30, 29, 28 }, 435 }, 436 437 [JZ4780_CLK_PCMPLL] = { 438 "pcm_pll", CGU_CLK_MUX | CGU_CLK_DIV, 439 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 440 JZ4780_CLK_EPLL, JZ4780_CLK_VPLL }, 441 .mux = { CGU_REG_PCMCDR, 29, 2 }, 442 .div = { CGU_REG_PCMCDR, 0, 1, 8, 28, 27, 26 }, 443 }, 444 445 [JZ4780_CLK_PCM] = { 446 "pcm", CGU_CLK_MUX | CGU_CLK_GATE, 447 .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -1 }, 448 .mux = { CGU_REG_PCMCDR, 31, 1 }, 449 .gate = { CGU_REG_CLKGR1, 3 }, 450 }, 451 452 [JZ4780_CLK_GPU] = { 453 "gpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, 454 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 455 JZ4780_CLK_EPLL }, 456 .mux = { CGU_REG_GPUCDR, 30, 2 }, 457 .div = { CGU_REG_GPUCDR, 0, 1, 4, 29, 28, 27 }, 458 .gate = { CGU_REG_CLKGR1, 4 }, 459 }, 460 461 [JZ4780_CLK_HDMI] = { 462 "hdmi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, 463 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 464 JZ4780_CLK_VPLL, -1 }, 465 .mux = { CGU_REG_HDMICDR, 30, 2 }, 466 .div = { CGU_REG_HDMICDR, 0, 1, 8, 29, 28, 26 }, 467 .gate = { CGU_REG_CLKGR1, 9 }, 468 }, 469 470 [JZ4780_CLK_BCH] = { 471 "bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, 472 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 473 JZ4780_CLK_EPLL }, 474 .mux = { CGU_REG_BCHCDR, 30, 2 }, 475 .div = { CGU_REG_BCHCDR, 0, 1, 4, 29, 28, 27 }, 476 .gate = { CGU_REG_CLKGR0, 1 }, 477 }, 478 479 /* Gate-only clocks */ 480 481 [JZ4780_CLK_NEMC] = { 482 "nemc", CGU_CLK_GATE, 483 .parents = { JZ4780_CLK_AHB2, -1, -1, -1 }, 484 .gate = { CGU_REG_CLKGR0, 0 }, 485 }, 486 487 [JZ4780_CLK_OTG0] = { 488 "otg0", CGU_CLK_GATE, 489 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 490 .gate = { CGU_REG_CLKGR0, 2 }, 491 }, 492 493 [JZ4780_CLK_SSI0] = { 494 "ssi0", CGU_CLK_GATE, 495 .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, 496 .gate = { CGU_REG_CLKGR0, 4 }, 497 }, 498 499 [JZ4780_CLK_SMB0] = { 500 "smb0", CGU_CLK_GATE, 501 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, 502 .gate = { CGU_REG_CLKGR0, 5 }, 503 }, 504 505 [JZ4780_CLK_SMB1] = { 506 "smb1", CGU_CLK_GATE, 507 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, 508 .gate = { CGU_REG_CLKGR0, 6 }, 509 }, 510 511 [JZ4780_CLK_SCC] = { 512 "scc", CGU_CLK_GATE, 513 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 514 .gate = { CGU_REG_CLKGR0, 7 }, 515 }, 516 517 [JZ4780_CLK_AIC] = { 518 "aic", CGU_CLK_GATE, 519 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 520 .gate = { CGU_REG_CLKGR0, 8 }, 521 }, 522 523 [JZ4780_CLK_TSSI0] = { 524 "tssi0", CGU_CLK_GATE, 525 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 526 .gate = { CGU_REG_CLKGR0, 9 }, 527 }, 528 529 [JZ4780_CLK_OWI] = { 530 "owi", CGU_CLK_GATE, 531 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 532 .gate = { CGU_REG_CLKGR0, 10 }, 533 }, 534 535 [JZ4780_CLK_KBC] = { 536 "kbc", CGU_CLK_GATE, 537 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 538 .gate = { CGU_REG_CLKGR0, 13 }, 539 }, 540 541 [JZ4780_CLK_SADC] = { 542 "sadc", CGU_CLK_GATE, 543 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 544 .gate = { CGU_REG_CLKGR0, 14 }, 545 }, 546 547 [JZ4780_CLK_UART0] = { 548 "uart0", CGU_CLK_GATE, 549 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 550 .gate = { CGU_REG_CLKGR0, 15 }, 551 }, 552 553 [JZ4780_CLK_UART1] = { 554 "uart1", CGU_CLK_GATE, 555 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 556 .gate = { CGU_REG_CLKGR0, 16 }, 557 }, 558 559 [JZ4780_CLK_UART2] = { 560 "uart2", CGU_CLK_GATE, 561 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 562 .gate = { CGU_REG_CLKGR0, 17 }, 563 }, 564 565 [JZ4780_CLK_UART3] = { 566 "uart3", CGU_CLK_GATE, 567 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 568 .gate = { CGU_REG_CLKGR0, 18 }, 569 }, 570 571 [JZ4780_CLK_SSI1] = { 572 "ssi1", CGU_CLK_GATE, 573 .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, 574 .gate = { CGU_REG_CLKGR0, 19 }, 575 }, 576 577 [JZ4780_CLK_SSI2] = { 578 "ssi2", CGU_CLK_GATE, 579 .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, 580 .gate = { CGU_REG_CLKGR0, 20 }, 581 }, 582 583 [JZ4780_CLK_PDMA] = { 584 "pdma", CGU_CLK_GATE, 585 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 586 .gate = { CGU_REG_CLKGR0, 21 }, 587 }, 588 589 [JZ4780_CLK_GPS] = { 590 "gps", CGU_CLK_GATE, 591 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 592 .gate = { CGU_REG_CLKGR0, 22 }, 593 }, 594 595 [JZ4780_CLK_MAC] = { 596 "mac", CGU_CLK_GATE, 597 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 598 .gate = { CGU_REG_CLKGR0, 23 }, 599 }, 600 601 [JZ4780_CLK_SMB2] = { 602 "smb2", CGU_CLK_GATE, 603 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, 604 .gate = { CGU_REG_CLKGR0, 24 }, 605 }, 606 607 [JZ4780_CLK_CIM] = { 608 "cim", CGU_CLK_GATE, 609 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 610 .gate = { CGU_REG_CLKGR0, 26 }, 611 }, 612 613 [JZ4780_CLK_LCD] = { 614 "lcd", CGU_CLK_GATE, 615 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 616 .gate = { CGU_REG_CLKGR0, 28 }, 617 }, 618 619 [JZ4780_CLK_TVE] = { 620 "tve", CGU_CLK_GATE, 621 .parents = { JZ4780_CLK_LCD, -1, -1, -1 }, 622 .gate = { CGU_REG_CLKGR0, 27 }, 623 }, 624 625 [JZ4780_CLK_IPU] = { 626 "ipu", CGU_CLK_GATE, 627 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 628 .gate = { CGU_REG_CLKGR0, 29 }, 629 }, 630 631 [JZ4780_CLK_DDR0] = { 632 "ddr0", CGU_CLK_GATE, 633 .parents = { JZ4780_CLK_DDR, -1, -1, -1 }, 634 .gate = { CGU_REG_CLKGR0, 30 }, 635 }, 636 637 [JZ4780_CLK_DDR1] = { 638 "ddr1", CGU_CLK_GATE, 639 .parents = { JZ4780_CLK_DDR, -1, -1, -1 }, 640 .gate = { CGU_REG_CLKGR0, 31 }, 641 }, 642 643 [JZ4780_CLK_SMB3] = { 644 "smb3", CGU_CLK_GATE, 645 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, 646 .gate = { CGU_REG_CLKGR1, 0 }, 647 }, 648 649 [JZ4780_CLK_TSSI1] = { 650 "tssi1", CGU_CLK_GATE, 651 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 652 .gate = { CGU_REG_CLKGR1, 1 }, 653 }, 654 655 [JZ4780_CLK_COMPRESS] = { 656 "compress", CGU_CLK_GATE, 657 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 658 .gate = { CGU_REG_CLKGR1, 5 }, 659 }, 660 661 [JZ4780_CLK_AIC1] = { 662 "aic1", CGU_CLK_GATE, 663 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 664 .gate = { CGU_REG_CLKGR1, 6 }, 665 }, 666 667 [JZ4780_CLK_GPVLC] = { 668 "gpvlc", CGU_CLK_GATE, 669 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 670 .gate = { CGU_REG_CLKGR1, 7 }, 671 }, 672 673 [JZ4780_CLK_OTG1] = { 674 "otg1", CGU_CLK_GATE, 675 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 676 .gate = { CGU_REG_CLKGR1, 8 }, 677 }, 678 679 [JZ4780_CLK_UART4] = { 680 "uart4", CGU_CLK_GATE, 681 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 682 .gate = { CGU_REG_CLKGR1, 10 }, 683 }, 684 685 [JZ4780_CLK_AHBMON] = { 686 "ahb_mon", CGU_CLK_GATE, 687 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 688 .gate = { CGU_REG_CLKGR1, 11 }, 689 }, 690 691 [JZ4780_CLK_SMB4] = { 692 "smb4", CGU_CLK_GATE, 693 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, 694 .gate = { CGU_REG_CLKGR1, 12 }, 695 }, 696 697 [JZ4780_CLK_DES] = { 698 "des", CGU_CLK_GATE, 699 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 700 .gate = { CGU_REG_CLKGR1, 13 }, 701 }, 702 703 [JZ4780_CLK_X2D] = { 704 "x2d", CGU_CLK_GATE, 705 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 706 .gate = { CGU_REG_CLKGR1, 14 }, 707 }, 708 709 [JZ4780_CLK_CORE1] = { 710 "core1", CGU_CLK_GATE, 711 .parents = { JZ4780_CLK_CPU, -1, -1, -1 }, 712 .gate = { CGU_REG_CLKGR1, 15 }, 713 }, 714 715 }; 716 717 static void __init jz4780_cgu_init(struct device_node *np) 718 { 719 int retval; 720 721 cgu = ingenic_cgu_new(jz4780_cgu_clocks, 722 ARRAY_SIZE(jz4780_cgu_clocks), np); 723 if (!cgu) { 724 pr_err("%s: failed to initialise CGU\n", __func__); 725 return; 726 } 727 728 retval = ingenic_cgu_register_clocks(cgu); 729 if (retval) { 730 pr_err("%s: failed to register CGU Clocks\n", __func__); 731 return; 732 } 733 } 734 CLK_OF_DECLARE(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init); 735