1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * JZ4770 SoC CGU driver 4 * Copyright 2018, Paul Cercueil <paul@crapouillou.net> 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/io.h> 11 #include <linux/of.h> 12 #include <linux/syscore_ops.h> 13 #include <dt-bindings/clock/jz4770-cgu.h> 14 #include "cgu.h" 15 16 /* 17 * CPM registers offset address definition 18 */ 19 #define CGU_REG_CPCCR 0x00 20 #define CGU_REG_LCR 0x04 21 #define CGU_REG_CPPCR0 0x10 22 #define CGU_REG_CLKGR0 0x20 23 #define CGU_REG_OPCR 0x24 24 #define CGU_REG_CLKGR1 0x28 25 #define CGU_REG_CPPCR1 0x30 26 #define CGU_REG_USBPCR1 0x48 27 #define CGU_REG_USBCDR 0x50 28 #define CGU_REG_I2SCDR 0x60 29 #define CGU_REG_LPCDR 0x64 30 #define CGU_REG_MSC0CDR 0x68 31 #define CGU_REG_UHCCDR 0x6c 32 #define CGU_REG_SSICDR 0x74 33 #define CGU_REG_CIMCDR 0x7c 34 #define CGU_REG_GPSCDR 0x80 35 #define CGU_REG_PCMCDR 0x84 36 #define CGU_REG_GPUCDR 0x88 37 #define CGU_REG_MSC1CDR 0xA4 38 #define CGU_REG_MSC2CDR 0xA8 39 #define CGU_REG_BCHCDR 0xAC 40 41 /* bits within the LCR register */ 42 #define LCR_LPM BIT(0) /* Low Power Mode */ 43 44 /* bits within the OPCR register */ 45 #define OPCR_SPENDH BIT(5) /* UHC PHY suspend */ 46 47 /* bits within the USBPCR1 register */ 48 #define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */ 49 50 static struct ingenic_cgu *cgu; 51 52 static int jz4770_uhc_phy_enable(struct clk_hw *hw) 53 { 54 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; 55 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; 56 57 writel(readl(reg_opcr) & ~OPCR_SPENDH, reg_opcr); 58 writel(readl(reg_usbpcr1) | USBPCR1_UHC_POWER, reg_usbpcr1); 59 return 0; 60 } 61 62 static void jz4770_uhc_phy_disable(struct clk_hw *hw) 63 { 64 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; 65 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; 66 67 writel(readl(reg_usbpcr1) & ~USBPCR1_UHC_POWER, reg_usbpcr1); 68 writel(readl(reg_opcr) | OPCR_SPENDH, reg_opcr); 69 } 70 71 static int jz4770_uhc_phy_is_enabled(struct clk_hw *hw) 72 { 73 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; 74 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; 75 76 return !(readl(reg_opcr) & OPCR_SPENDH) && 77 (readl(reg_usbpcr1) & USBPCR1_UHC_POWER); 78 } 79 80 static const struct clk_ops jz4770_uhc_phy_ops = { 81 .enable = jz4770_uhc_phy_enable, 82 .disable = jz4770_uhc_phy_disable, 83 .is_enabled = jz4770_uhc_phy_is_enabled, 84 }; 85 86 static const s8 pll_od_encoding[8] = { 87 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, 88 }; 89 90 static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { 91 92 /* External clocks */ 93 94 [JZ4770_CLK_EXT] = { "ext", CGU_CLK_EXT }, 95 [JZ4770_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT }, 96 97 /* PLLs */ 98 99 [JZ4770_CLK_PLL0] = { 100 "pll0", CGU_CLK_PLL, 101 .parents = { JZ4770_CLK_EXT }, 102 .pll = { 103 .reg = CGU_REG_CPPCR0, 104 .m_shift = 24, 105 .m_bits = 7, 106 .m_offset = 1, 107 .n_shift = 18, 108 .n_bits = 5, 109 .n_offset = 1, 110 .od_shift = 16, 111 .od_bits = 2, 112 .od_max = 8, 113 .od_encoding = pll_od_encoding, 114 .bypass_bit = 9, 115 .enable_bit = 8, 116 .stable_bit = 10, 117 }, 118 }, 119 120 [JZ4770_CLK_PLL1] = { 121 /* TODO: PLL1 can depend on PLL0 */ 122 "pll1", CGU_CLK_PLL, 123 .parents = { JZ4770_CLK_EXT }, 124 .pll = { 125 .reg = CGU_REG_CPPCR1, 126 .m_shift = 24, 127 .m_bits = 7, 128 .m_offset = 1, 129 .n_shift = 18, 130 .n_bits = 5, 131 .n_offset = 1, 132 .od_shift = 16, 133 .od_bits = 2, 134 .od_max = 8, 135 .od_encoding = pll_od_encoding, 136 .enable_bit = 7, 137 .stable_bit = 6, 138 .no_bypass_bit = true, 139 }, 140 }, 141 142 /* Main clocks */ 143 144 [JZ4770_CLK_CCLK] = { 145 "cclk", CGU_CLK_DIV, 146 .parents = { JZ4770_CLK_PLL0, }, 147 .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, 148 }, 149 [JZ4770_CLK_H0CLK] = { 150 "h0clk", CGU_CLK_DIV, 151 .parents = { JZ4770_CLK_PLL0, }, 152 .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, 153 }, 154 [JZ4770_CLK_H1CLK] = { 155 "h1clk", CGU_CLK_DIV | CGU_CLK_GATE, 156 .parents = { JZ4770_CLK_PLL0, }, 157 .div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1 }, 158 .gate = { CGU_REG_CLKGR1, 7 }, 159 }, 160 [JZ4770_CLK_H2CLK] = { 161 "h2clk", CGU_CLK_DIV, 162 .parents = { JZ4770_CLK_PLL0, }, 163 .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 }, 164 }, 165 [JZ4770_CLK_C1CLK] = { 166 "c1clk", CGU_CLK_DIV | CGU_CLK_GATE, 167 .parents = { JZ4770_CLK_PLL0, }, 168 .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 }, 169 .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle 170 }, 171 [JZ4770_CLK_PCLK] = { 172 "pclk", CGU_CLK_DIV, 173 .parents = { JZ4770_CLK_PLL0, }, 174 .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 }, 175 }, 176 177 /* Those divided clocks can connect to PLL0 or PLL1 */ 178 179 [JZ4770_CLK_MMC0_MUX] = { 180 "mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, 181 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, 182 .mux = { CGU_REG_MSC0CDR, 30, 1 }, 183 .div = { CGU_REG_MSC0CDR, 0, 1, 7, -1, -1, 31 }, 184 .gate = { CGU_REG_MSC0CDR, 31 }, 185 }, 186 [JZ4770_CLK_MMC1_MUX] = { 187 "mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, 188 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, 189 .mux = { CGU_REG_MSC1CDR, 30, 1 }, 190 .div = { CGU_REG_MSC1CDR, 0, 1, 7, -1, -1, 31 }, 191 .gate = { CGU_REG_MSC1CDR, 31 }, 192 }, 193 [JZ4770_CLK_MMC2_MUX] = { 194 "mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, 195 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, 196 .mux = { CGU_REG_MSC2CDR, 30, 1 }, 197 .div = { CGU_REG_MSC2CDR, 0, 1, 7, -1, -1, 31 }, 198 .gate = { CGU_REG_MSC2CDR, 31 }, 199 }, 200 [JZ4770_CLK_CIM] = { 201 "cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, 202 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, 203 .mux = { CGU_REG_CIMCDR, 31, 1 }, 204 .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 }, 205 .gate = { CGU_REG_CLKGR0, 26 }, 206 }, 207 [JZ4770_CLK_UHC] = { 208 "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, 209 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, 210 .mux = { CGU_REG_UHCCDR, 29, 1 }, 211 .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 }, 212 .gate = { CGU_REG_CLKGR0, 24 }, 213 }, 214 [JZ4770_CLK_GPU] = { 215 "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, 216 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, -1 }, 217 .mux = { CGU_REG_GPUCDR, 31, 1 }, 218 .div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 }, 219 .gate = { CGU_REG_CLKGR1, 9 }, 220 }, 221 [JZ4770_CLK_BCH] = { 222 "bch", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, 223 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, 224 .mux = { CGU_REG_BCHCDR, 31, 1 }, 225 .div = { CGU_REG_BCHCDR, 0, 1, 3, -1, -1, -1 }, 226 .gate = { CGU_REG_CLKGR0, 1 }, 227 }, 228 [JZ4770_CLK_LPCLK_MUX] = { 229 "lpclk", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, 230 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, 231 .mux = { CGU_REG_LPCDR, 29, 1 }, 232 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, 233 .gate = { CGU_REG_CLKGR0, 28 }, 234 }, 235 [JZ4770_CLK_GPS] = { 236 "gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, 237 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, 238 .mux = { CGU_REG_GPSCDR, 31, 1 }, 239 .div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 }, 240 .gate = { CGU_REG_CLKGR0, 22 }, 241 }, 242 243 /* Those divided clocks can connect to EXT, PLL0 or PLL1 */ 244 245 [JZ4770_CLK_SSI_MUX] = { 246 "ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX, 247 .parents = { JZ4770_CLK_EXT, -1, 248 JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, 249 .mux = { CGU_REG_SSICDR, 30, 2 }, 250 .div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1 }, 251 }, 252 [JZ4770_CLK_PCM_MUX] = { 253 "pcm_mux", CGU_CLK_DIV | CGU_CLK_MUX, 254 .parents = { JZ4770_CLK_EXT, -1, 255 JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, 256 .mux = { CGU_REG_PCMCDR, 30, 2 }, 257 .div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1 }, 258 }, 259 [JZ4770_CLK_I2S] = { 260 "i2s", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, 261 .parents = { JZ4770_CLK_EXT, -1, 262 JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, 263 .mux = { CGU_REG_I2SCDR, 30, 2 }, 264 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, 265 .gate = { CGU_REG_CLKGR1, 13 }, 266 }, 267 [JZ4770_CLK_OTG] = { 268 "usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, 269 .parents = { JZ4770_CLK_EXT, -1, 270 JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, 271 .mux = { CGU_REG_USBCDR, 30, 2 }, 272 .div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 }, 273 .gate = { CGU_REG_CLKGR0, 2 }, 274 }, 275 276 /* Gate-only clocks */ 277 278 [JZ4770_CLK_SSI0] = { 279 "ssi0", CGU_CLK_GATE, 280 .parents = { JZ4770_CLK_SSI_MUX, }, 281 .gate = { CGU_REG_CLKGR0, 4 }, 282 }, 283 [JZ4770_CLK_SSI1] = { 284 "ssi1", CGU_CLK_GATE, 285 .parents = { JZ4770_CLK_SSI_MUX, }, 286 .gate = { CGU_REG_CLKGR0, 19 }, 287 }, 288 [JZ4770_CLK_SSI2] = { 289 "ssi2", CGU_CLK_GATE, 290 .parents = { JZ4770_CLK_SSI_MUX, }, 291 .gate = { CGU_REG_CLKGR0, 20 }, 292 }, 293 [JZ4770_CLK_PCM0] = { 294 "pcm0", CGU_CLK_GATE, 295 .parents = { JZ4770_CLK_PCM_MUX, }, 296 .gate = { CGU_REG_CLKGR1, 8 }, 297 }, 298 [JZ4770_CLK_PCM1] = { 299 "pcm1", CGU_CLK_GATE, 300 .parents = { JZ4770_CLK_PCM_MUX, }, 301 .gate = { CGU_REG_CLKGR1, 10 }, 302 }, 303 [JZ4770_CLK_DMA] = { 304 "dma", CGU_CLK_GATE, 305 .parents = { JZ4770_CLK_H2CLK, }, 306 .gate = { CGU_REG_CLKGR0, 21 }, 307 }, 308 [JZ4770_CLK_I2C0] = { 309 "i2c0", CGU_CLK_GATE, 310 .parents = { JZ4770_CLK_EXT, }, 311 .gate = { CGU_REG_CLKGR0, 5 }, 312 }, 313 [JZ4770_CLK_I2C1] = { 314 "i2c1", CGU_CLK_GATE, 315 .parents = { JZ4770_CLK_EXT, }, 316 .gate = { CGU_REG_CLKGR0, 6 }, 317 }, 318 [JZ4770_CLK_I2C2] = { 319 "i2c2", CGU_CLK_GATE, 320 .parents = { JZ4770_CLK_EXT, }, 321 .gate = { CGU_REG_CLKGR1, 15 }, 322 }, 323 [JZ4770_CLK_UART0] = { 324 "uart0", CGU_CLK_GATE, 325 .parents = { JZ4770_CLK_EXT, }, 326 .gate = { CGU_REG_CLKGR0, 15 }, 327 }, 328 [JZ4770_CLK_UART1] = { 329 "uart1", CGU_CLK_GATE, 330 .parents = { JZ4770_CLK_EXT, }, 331 .gate = { CGU_REG_CLKGR0, 16 }, 332 }, 333 [JZ4770_CLK_UART2] = { 334 "uart2", CGU_CLK_GATE, 335 .parents = { JZ4770_CLK_EXT, }, 336 .gate = { CGU_REG_CLKGR0, 17 }, 337 }, 338 [JZ4770_CLK_UART3] = { 339 "uart3", CGU_CLK_GATE, 340 .parents = { JZ4770_CLK_EXT, }, 341 .gate = { CGU_REG_CLKGR0, 18 }, 342 }, 343 [JZ4770_CLK_IPU] = { 344 "ipu", CGU_CLK_GATE, 345 .parents = { JZ4770_CLK_H0CLK, }, 346 .gate = { CGU_REG_CLKGR0, 29 }, 347 }, 348 [JZ4770_CLK_ADC] = { 349 "adc", CGU_CLK_GATE, 350 .parents = { JZ4770_CLK_EXT, }, 351 .gate = { CGU_REG_CLKGR0, 14 }, 352 }, 353 [JZ4770_CLK_AIC] = { 354 "aic", CGU_CLK_GATE, 355 .parents = { JZ4770_CLK_EXT, }, 356 .gate = { CGU_REG_CLKGR0, 8 }, 357 }, 358 [JZ4770_CLK_AUX] = { 359 "aux", CGU_CLK_GATE, 360 .parents = { JZ4770_CLK_C1CLK, }, 361 .gate = { CGU_REG_CLKGR1, 14 }, 362 }, 363 [JZ4770_CLK_VPU] = { 364 "vpu", CGU_CLK_GATE, 365 .parents = { JZ4770_CLK_H1CLK, }, 366 .gate = { CGU_REG_LCR, 30, false, 150 }, 367 }, 368 [JZ4770_CLK_MMC0] = { 369 "mmc0", CGU_CLK_GATE, 370 .parents = { JZ4770_CLK_MMC0_MUX, }, 371 .gate = { CGU_REG_CLKGR0, 3 }, 372 }, 373 [JZ4770_CLK_MMC1] = { 374 "mmc1", CGU_CLK_GATE, 375 .parents = { JZ4770_CLK_MMC1_MUX, }, 376 .gate = { CGU_REG_CLKGR0, 11 }, 377 }, 378 [JZ4770_CLK_MMC2] = { 379 "mmc2", CGU_CLK_GATE, 380 .parents = { JZ4770_CLK_MMC2_MUX, }, 381 .gate = { CGU_REG_CLKGR0, 12 }, 382 }, 383 [JZ4770_CLK_OTG_PHY] = { 384 "usb_phy", CGU_CLK_GATE, 385 .parents = { JZ4770_CLK_OTG }, 386 .gate = { CGU_REG_OPCR, 7, true, 50 }, 387 }, 388 389 /* Custom clocks */ 390 391 [JZ4770_CLK_UHC_PHY] = { 392 "uhc_phy", CGU_CLK_CUSTOM, 393 .parents = { JZ4770_CLK_UHC, -1, -1, -1 }, 394 .custom = { &jz4770_uhc_phy_ops }, 395 }, 396 397 [JZ4770_CLK_EXT512] = { 398 "ext/512", CGU_CLK_FIXDIV, 399 .parents = { JZ4770_CLK_EXT }, 400 .fixdiv = { 512 }, 401 }, 402 403 [JZ4770_CLK_RTC] = { 404 "rtc", CGU_CLK_MUX, 405 .parents = { JZ4770_CLK_EXT512, JZ4770_CLK_OSC32K, }, 406 .mux = { CGU_REG_OPCR, 2, 1}, 407 }, 408 }; 409 410 #if IS_ENABLED(CONFIG_PM_SLEEP) 411 static int jz4770_cgu_pm_suspend(void) 412 { 413 u32 val; 414 415 val = readl(cgu->base + CGU_REG_LCR); 416 writel(val | LCR_LPM, cgu->base + CGU_REG_LCR); 417 return 0; 418 } 419 420 static void jz4770_cgu_pm_resume(void) 421 { 422 u32 val; 423 424 val = readl(cgu->base + CGU_REG_LCR); 425 writel(val & ~LCR_LPM, cgu->base + CGU_REG_LCR); 426 } 427 428 static struct syscore_ops jz4770_cgu_pm_ops = { 429 .suspend = jz4770_cgu_pm_suspend, 430 .resume = jz4770_cgu_pm_resume, 431 }; 432 #endif /* CONFIG_PM_SLEEP */ 433 434 static void __init jz4770_cgu_init(struct device_node *np) 435 { 436 int retval; 437 438 cgu = ingenic_cgu_new(jz4770_cgu_clocks, 439 ARRAY_SIZE(jz4770_cgu_clocks), np); 440 if (!cgu) 441 pr_err("%s: failed to initialise CGU\n", __func__); 442 443 retval = ingenic_cgu_register_clocks(cgu); 444 if (retval) 445 pr_err("%s: failed to register CGU Clocks\n", __func__); 446 447 #if IS_ENABLED(CONFIG_PM_SLEEP) 448 register_syscore_ops(&jz4770_cgu_pm_ops); 449 #endif 450 } 451 452 /* We only probe via devicetree, no need for a platform driver */ 453 CLK_OF_DECLARE(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init); 454