1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Ingenic JZ4740 SoC CGU driver 4 * 5 * Copyright (c) 2015 Imagination Technologies 6 * Author: Paul Burton <paul.burton@mips.com> 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/delay.h> 11 #include <linux/io.h> 12 #include <linux/of.h> 13 #include <dt-bindings/clock/jz4740-cgu.h> 14 #include "cgu.h" 15 #include "pm.h" 16 17 /* CGU register offsets */ 18 #define CGU_REG_CPCCR 0x00 19 #define CGU_REG_LCR 0x04 20 #define CGU_REG_CPPCR 0x10 21 #define CGU_REG_CLKGR 0x20 22 #define CGU_REG_SCR 0x24 23 #define CGU_REG_I2SCDR 0x60 24 #define CGU_REG_LPCDR 0x64 25 #define CGU_REG_MSCCDR 0x68 26 #define CGU_REG_UHCCDR 0x6c 27 #define CGU_REG_SSICDR 0x74 28 29 /* bits within a PLL control register */ 30 #define PLLCTL_M_SHIFT 23 31 #define PLLCTL_M_MASK (0x1ff << PLLCTL_M_SHIFT) 32 #define PLLCTL_N_SHIFT 18 33 #define PLLCTL_N_MASK (0x1f << PLLCTL_N_SHIFT) 34 #define PLLCTL_OD_SHIFT 16 35 #define PLLCTL_OD_MASK (0x3 << PLLCTL_OD_SHIFT) 36 #define PLLCTL_STABLE (1 << 10) 37 #define PLLCTL_BYPASS (1 << 9) 38 #define PLLCTL_ENABLE (1 << 8) 39 40 /* bits within the LCR register */ 41 #define LCR_SLEEP (1 << 0) 42 43 /* bits within the CLKGR register */ 44 #define CLKGR_UDC (1 << 11) 45 46 static struct ingenic_cgu *cgu; 47 48 static const s8 pll_od_encoding[4] = { 49 0x0, 0x1, -1, 0x3, 50 }; 51 52 static const u8 jz4740_cgu_cpccr_div_table[] = { 53 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 54 }; 55 56 static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { 57 58 /* External clocks */ 59 60 [JZ4740_CLK_EXT] = { "ext", CGU_CLK_EXT }, 61 [JZ4740_CLK_RTC] = { "rtc", CGU_CLK_EXT }, 62 63 [JZ4740_CLK_PLL] = { 64 "pll", CGU_CLK_PLL, 65 .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, 66 .pll = { 67 .reg = CGU_REG_CPPCR, 68 .m_shift = 23, 69 .m_bits = 9, 70 .m_offset = 2, 71 .n_shift = 18, 72 .n_bits = 5, 73 .n_offset = 2, 74 .od_shift = 16, 75 .od_bits = 2, 76 .od_max = 4, 77 .od_encoding = pll_od_encoding, 78 .stable_bit = 10, 79 .bypass_bit = 9, 80 .enable_bit = 8, 81 }, 82 }, 83 84 /* Muxes & dividers */ 85 86 [JZ4740_CLK_PLL_HALF] = { 87 "pll half", CGU_CLK_DIV, 88 .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, 89 .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 }, 90 }, 91 92 [JZ4740_CLK_CCLK] = { 93 "cclk", CGU_CLK_DIV, 94 .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, 95 .div = { 96 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 97 jz4740_cgu_cpccr_div_table, 98 }, 99 }, 100 101 [JZ4740_CLK_HCLK] = { 102 "hclk", CGU_CLK_DIV, 103 .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, 104 .div = { 105 CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 106 jz4740_cgu_cpccr_div_table, 107 }, 108 }, 109 110 [JZ4740_CLK_PCLK] = { 111 "pclk", CGU_CLK_DIV, 112 .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, 113 .div = { 114 CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 115 jz4740_cgu_cpccr_div_table, 116 }, 117 }, 118 119 [JZ4740_CLK_MCLK] = { 120 "mclk", CGU_CLK_DIV, 121 .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, 122 .div = { 123 CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 124 jz4740_cgu_cpccr_div_table, 125 }, 126 }, 127 128 [JZ4740_CLK_LCD] = { 129 "lcd", CGU_CLK_DIV | CGU_CLK_GATE, 130 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, 131 .div = { 132 CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1, 133 jz4740_cgu_cpccr_div_table, 134 }, 135 .gate = { CGU_REG_CLKGR, 10 }, 136 }, 137 138 [JZ4740_CLK_LCD_PCLK] = { 139 "lcd_pclk", CGU_CLK_DIV, 140 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, 141 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, 142 }, 143 144 [JZ4740_CLK_I2S] = { 145 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, 146 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 }, 147 .mux = { CGU_REG_CPCCR, 31, 1 }, 148 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, 149 .gate = { CGU_REG_CLKGR, 6 }, 150 }, 151 152 [JZ4740_CLK_SPI] = { 153 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, 154 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 }, 155 .mux = { CGU_REG_SSICDR, 31, 1 }, 156 .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 }, 157 .gate = { CGU_REG_CLKGR, 4 }, 158 }, 159 160 [JZ4740_CLK_MMC] = { 161 "mmc", CGU_CLK_DIV | CGU_CLK_GATE, 162 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, 163 .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 }, 164 .gate = { CGU_REG_CLKGR, 7 }, 165 }, 166 167 [JZ4740_CLK_UHC] = { 168 "uhc", CGU_CLK_DIV | CGU_CLK_GATE, 169 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, 170 .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 }, 171 .gate = { CGU_REG_CLKGR, 14 }, 172 }, 173 174 [JZ4740_CLK_UDC] = { 175 "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, 176 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 }, 177 .mux = { CGU_REG_CPCCR, 29, 1 }, 178 .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, 179 .gate = { CGU_REG_SCR, 6, true }, 180 }, 181 182 /* Gate-only clocks */ 183 184 [JZ4740_CLK_UART0] = { 185 "uart0", CGU_CLK_GATE, 186 .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, 187 .gate = { CGU_REG_CLKGR, 0 }, 188 }, 189 190 [JZ4740_CLK_UART1] = { 191 "uart1", CGU_CLK_GATE, 192 .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, 193 .gate = { CGU_REG_CLKGR, 15 }, 194 }, 195 196 [JZ4740_CLK_DMA] = { 197 "dma", CGU_CLK_GATE, 198 .parents = { JZ4740_CLK_PCLK, -1, -1, -1 }, 199 .gate = { CGU_REG_CLKGR, 12 }, 200 }, 201 202 [JZ4740_CLK_IPU] = { 203 "ipu", CGU_CLK_GATE, 204 .parents = { JZ4740_CLK_PCLK, -1, -1, -1 }, 205 .gate = { CGU_REG_CLKGR, 13 }, 206 }, 207 208 [JZ4740_CLK_ADC] = { 209 "adc", CGU_CLK_GATE, 210 .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, 211 .gate = { CGU_REG_CLKGR, 8 }, 212 }, 213 214 [JZ4740_CLK_I2C] = { 215 "i2c", CGU_CLK_GATE, 216 .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, 217 .gate = { CGU_REG_CLKGR, 3 }, 218 }, 219 220 [JZ4740_CLK_AIC] = { 221 "aic", CGU_CLK_GATE, 222 .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, 223 .gate = { CGU_REG_CLKGR, 5 }, 224 }, 225 }; 226 227 static void __init jz4740_cgu_init(struct device_node *np) 228 { 229 int retval; 230 231 cgu = ingenic_cgu_new(jz4740_cgu_clocks, 232 ARRAY_SIZE(jz4740_cgu_clocks), np); 233 if (!cgu) { 234 pr_err("%s: failed to initialise CGU\n", __func__); 235 return; 236 } 237 238 retval = ingenic_cgu_register_clocks(cgu); 239 if (retval) 240 pr_err("%s: failed to register CGU Clocks\n", __func__); 241 242 ingenic_cgu_register_syscore_ops(cgu); 243 } 244 CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init); 245