1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Ingenic SoC CGU driver 4 * 5 * Copyright (c) 2013-2015 Imagination Technologies 6 * Author: Paul Burton <paul.burton@mips.com> 7 */ 8 9 #ifndef __DRIVERS_CLK_INGENIC_CGU_H__ 10 #define __DRIVERS_CLK_INGENIC_CGU_H__ 11 12 #include <linux/bitops.h> 13 #include <linux/clk-provider.h> 14 #include <linux/of.h> 15 #include <linux/spinlock.h> 16 17 /** 18 * struct ingenic_cgu_pll_info - information about a PLL 19 * @reg: the offset of the PLL's control register within the CGU 20 * @rate_multiplier: the multiplier needed by pll rate calculation 21 * @m_shift: the number of bits to shift the multiplier value by (ie. the 22 * index of the lowest bit of the multiplier value in the PLL's 23 * control register) 24 * @m_bits: the size of the multiplier field in bits 25 * @m_offset: the multiplier value which encodes to 0 in the PLL's control 26 * register 27 * @n_shift: the number of bits to shift the divider value by (ie. the 28 * index of the lowest bit of the divider value in the PLL's 29 * control register) 30 * @n_bits: the size of the divider field in bits 31 * @n_offset: the divider value which encodes to 0 in the PLL's control 32 * register 33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie. 34 * the index of the lowest bit of the post-VCO divider value in 35 * the PLL's control register) 36 * @od_bits: the size of the post-VCO divider field in bits, or 0 if no 37 * OD field exists (then the OD is fixed to 1) 38 * @od_max: the maximum post-VCO divider value 39 * @od_encoding: a pointer to an array mapping post-VCO divider values to 40 * their encoded values in the PLL control register, or -1 for 41 * unsupported values 42 * @bypass_reg: the offset of the bypass control register within the CGU 43 * @bypass_bit: the index of the bypass bit in the PLL control register, or 44 * -1 if there is no bypass bit 45 * @enable_bit: the index of the enable bit in the PLL control register, or 46 * -1 if there is no enable bit (ie, the PLL is always on) 47 * @stable_bit: the index of the stable bit in the PLL control register, or 48 * -1 if there is no stable bit 49 * @set_rate_hook: hook called immediately after updating the CGU register, 50 * before releasing the spinlock 51 */ 52 struct ingenic_cgu_pll_info { 53 unsigned reg; 54 unsigned rate_multiplier; 55 const s8 *od_encoding; 56 u8 m_shift, m_bits, m_offset; 57 u8 n_shift, n_bits, n_offset; 58 u8 od_shift, od_bits, od_max; 59 unsigned bypass_reg; 60 s8 bypass_bit; 61 s8 enable_bit; 62 s8 stable_bit; 63 void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, 64 unsigned long rate, unsigned long parent_rate, 65 unsigned int *m, unsigned int *n, unsigned int *od); 66 void (*set_rate_hook)(const struct ingenic_cgu_pll_info *pll_info, 67 unsigned long rate, unsigned long parent_rate); 68 }; 69 70 /** 71 * struct ingenic_cgu_mux_info - information about a clock mux 72 * @reg: offset of the mux control register within the CGU 73 * @shift: number of bits to shift the mux value by (ie. the index of 74 * the lowest bit of the mux value within its control register) 75 * @bits: the size of the mux value in bits 76 */ 77 struct ingenic_cgu_mux_info { 78 unsigned reg; 79 u8 shift; 80 u8 bits; 81 }; 82 83 /** 84 * struct ingenic_cgu_div_info - information about a divider 85 * @reg: offset of the divider control register within the CGU 86 * @shift: number of bits to left shift the divide value by (ie. the index of 87 * the lowest bit of the divide value within its control register) 88 * @div: number to divide the divider value by (i.e. if the 89 * effective divider value is the value written to the register 90 * multiplied by some constant) 91 * @bits: the size of the divide value in bits 92 * @ce_bit: the index of the change enable bit within reg, or -1 if there 93 * isn't one 94 * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one 95 * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one 96 * @bypass_mask: mask of parent clocks for which the divider does not apply 97 * @div_table: optional table to map the value read from the register to the 98 * actual divider value 99 */ 100 struct ingenic_cgu_div_info { 101 unsigned reg; 102 u8 shift; 103 u8 div; 104 u8 bits; 105 s8 ce_bit; 106 s8 busy_bit; 107 s8 stop_bit; 108 u8 bypass_mask; 109 const u8 *div_table; 110 }; 111 112 /** 113 * struct ingenic_cgu_fixdiv_info - information about a fixed divider 114 * @div: the divider applied to the parent clock 115 */ 116 struct ingenic_cgu_fixdiv_info { 117 unsigned div; 118 }; 119 120 /** 121 * struct ingenic_cgu_gate_info - information about a clock gate 122 * @reg: offset of the gate control register within the CGU 123 * @bit: offset of the bit in the register that controls the gate 124 * @clear_to_gate: if set, the clock is gated when the bit is cleared 125 * @delay_us: delay in microseconds after which the clock is considered stable 126 */ 127 struct ingenic_cgu_gate_info { 128 unsigned reg; 129 u8 bit; 130 bool clear_to_gate; 131 u16 delay_us; 132 }; 133 134 /** 135 * struct ingenic_cgu_custom_info - information about a custom (SoC) clock 136 * @clk_ops: custom clock operation callbacks 137 */ 138 struct ingenic_cgu_custom_info { 139 const struct clk_ops *clk_ops; 140 }; 141 142 /** 143 * struct ingenic_cgu_clk_info - information about a clock 144 * @name: name of the clock 145 * @type: a bitmask formed from CGU_CLK_* values 146 * @flags: common clock flags to set on this clock 147 * @parents: an array of the indices of potential parents of this clock 148 * within the clock_info array of the CGU, or -1 in entries 149 * which correspond to no valid parent 150 * @pll: information valid if type includes CGU_CLK_PLL 151 * @gate: information valid if type includes CGU_CLK_GATE 152 * @mux: information valid if type includes CGU_CLK_MUX 153 * @div: information valid if type includes CGU_CLK_DIV 154 * @fixdiv: information valid if type includes CGU_CLK_FIXDIV 155 * @custom: information valid if type includes CGU_CLK_CUSTOM 156 */ 157 struct ingenic_cgu_clk_info { 158 const char *name; 159 160 enum { 161 CGU_CLK_NONE = 0, 162 CGU_CLK_EXT = BIT(0), 163 CGU_CLK_PLL = BIT(1), 164 CGU_CLK_GATE = BIT(2), 165 CGU_CLK_MUX = BIT(3), 166 CGU_CLK_MUX_GLITCHFREE = BIT(4), 167 CGU_CLK_DIV = BIT(5), 168 CGU_CLK_FIXDIV = BIT(6), 169 CGU_CLK_CUSTOM = BIT(7), 170 } type; 171 172 unsigned long flags; 173 174 int parents[4]; 175 176 union { 177 struct ingenic_cgu_pll_info pll; 178 179 struct { 180 struct ingenic_cgu_gate_info gate; 181 struct ingenic_cgu_mux_info mux; 182 struct ingenic_cgu_div_info div; 183 struct ingenic_cgu_fixdiv_info fixdiv; 184 }; 185 186 struct ingenic_cgu_custom_info custom; 187 }; 188 }; 189 190 /** 191 * struct ingenic_cgu - data about the CGU 192 * @np: the device tree node that caused the CGU to be probed 193 * @base: the ioremap'ed base address of the CGU registers 194 * @clock_info: an array containing information about implemented clocks 195 * @clocks: used to provide clocks to DT, allows lookup of struct clk* 196 * @lock: lock to be held whilst manipulating CGU registers 197 */ 198 struct ingenic_cgu { 199 struct device_node *np; 200 void __iomem *base; 201 202 const struct ingenic_cgu_clk_info *clock_info; 203 struct clk_onecell_data clocks; 204 205 spinlock_t lock; 206 }; 207 208 /** 209 * struct ingenic_clk - private data for a clock 210 * @hw: see Documentation/driver-api/clk.rst 211 * @cgu: a pointer to the CGU data 212 * @idx: the index of this clock in cgu->clock_info 213 */ 214 struct ingenic_clk { 215 struct clk_hw hw; 216 struct ingenic_cgu *cgu; 217 unsigned idx; 218 }; 219 220 #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) 221 222 /** 223 * ingenic_cgu_new() - create a new CGU instance 224 * @clock_info: an array of clock information structures describing the clocks 225 * which are implemented by the CGU 226 * @num_clocks: the number of entries in clock_info 227 * @np: the device tree node which causes this CGU to be probed 228 * 229 * Return: a pointer to the CGU instance if initialisation is successful, 230 * otherwise NULL. 231 */ 232 struct ingenic_cgu * 233 ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, 234 unsigned num_clocks, struct device_node *np); 235 236 /** 237 * ingenic_cgu_register_clocks() - Registers the clocks 238 * @cgu: pointer to cgu data 239 * 240 * Register the clocks described by the CGU with the common clock framework. 241 * 242 * Return: 0 on success or -errno if unsuccesful. 243 */ 244 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); 245 246 #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */ 247