1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Ingenic SoC CGU driver 4 * 5 * Copyright (c) 2013-2015 Imagination Technologies 6 * Author: Paul Burton <paul.burton@mips.com> 7 */ 8 9 #ifndef __DRIVERS_CLK_INGENIC_CGU_H__ 10 #define __DRIVERS_CLK_INGENIC_CGU_H__ 11 12 #include <linux/bitops.h> 13 #include <linux/clk-provider.h> 14 #include <linux/of.h> 15 #include <linux/spinlock.h> 16 17 /** 18 * struct ingenic_cgu_pll_info - information about a PLL 19 * @reg: the offset of the PLL's control register within the CGU 20 * @rate_multiplier: the multiplier needed by pll rate calculation 21 * @m_shift: the number of bits to shift the multiplier value by (ie. the 22 * index of the lowest bit of the multiplier value in the PLL's 23 * control register) 24 * @m_bits: the size of the multiplier field in bits 25 * @m_offset: the multiplier value which encodes to 0 in the PLL's control 26 * register 27 * @n_shift: the number of bits to shift the divider value by (ie. the 28 * index of the lowest bit of the divider value in the PLL's 29 * control register) 30 * @n_bits: the size of the divider field in bits 31 * @n_offset: the divider value which encodes to 0 in the PLL's control 32 * register 33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie. 34 * the index of the lowest bit of the post-VCO divider value in 35 * the PLL's control register) 36 * @od_bits: the size of the post-VCO divider field in bits, or 0 if no 37 * OD field exists (then the OD is fixed to 1) 38 * @od_max: the maximum post-VCO divider value 39 * @od_encoding: a pointer to an array mapping post-VCO divider values to 40 * their encoded values in the PLL control register, or -1 for 41 * unsupported values 42 * @bypass_reg: the offset of the bypass control register within the CGU 43 * @bypass_bit: the index of the bypass bit in the PLL control register, or 44 * -1 if there is no bypass bit 45 * @enable_bit: the index of the enable bit in the PLL control register, or 46 * -1 if there is no enable bit (ie, the PLL is always on) 47 * @stable_bit: the index of the stable bit in the PLL control register, or 48 * -1 if there is no stable bit 49 */ 50 struct ingenic_cgu_pll_info { 51 unsigned reg; 52 unsigned rate_multiplier; 53 const s8 *od_encoding; 54 u8 m_shift, m_bits, m_offset; 55 u8 n_shift, n_bits, n_offset; 56 u8 od_shift, od_bits, od_max; 57 unsigned bypass_reg; 58 s8 bypass_bit; 59 s8 enable_bit; 60 s8 stable_bit; 61 void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, 62 unsigned long rate, unsigned long parent_rate, 63 unsigned int *m, unsigned int *n, unsigned int *od); 64 }; 65 66 /** 67 * struct ingenic_cgu_mux_info - information about a clock mux 68 * @reg: offset of the mux control register within the CGU 69 * @shift: number of bits to shift the mux value by (ie. the index of 70 * the lowest bit of the mux value within its control register) 71 * @bits: the size of the mux value in bits 72 */ 73 struct ingenic_cgu_mux_info { 74 unsigned reg; 75 u8 shift; 76 u8 bits; 77 }; 78 79 /** 80 * struct ingenic_cgu_div_info - information about a divider 81 * @reg: offset of the divider control register within the CGU 82 * @shift: number of bits to left shift the divide value by (ie. the index of 83 * the lowest bit of the divide value within its control register) 84 * @div: number to divide the divider value by (i.e. if the 85 * effective divider value is the value written to the register 86 * multiplied by some constant) 87 * @bits: the size of the divide value in bits 88 * @ce_bit: the index of the change enable bit within reg, or -1 if there 89 * isn't one 90 * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one 91 * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one 92 * @bypass_mask: mask of parent clocks for which the divider does not apply 93 * @div_table: optional table to map the value read from the register to the 94 * actual divider value 95 */ 96 struct ingenic_cgu_div_info { 97 unsigned reg; 98 u8 shift; 99 u8 div; 100 u8 bits; 101 s8 ce_bit; 102 s8 busy_bit; 103 s8 stop_bit; 104 u8 bypass_mask; 105 const u8 *div_table; 106 }; 107 108 /** 109 * struct ingenic_cgu_fixdiv_info - information about a fixed divider 110 * @div: the divider applied to the parent clock 111 */ 112 struct ingenic_cgu_fixdiv_info { 113 unsigned div; 114 }; 115 116 /** 117 * struct ingenic_cgu_gate_info - information about a clock gate 118 * @reg: offset of the gate control register within the CGU 119 * @bit: offset of the bit in the register that controls the gate 120 * @clear_to_gate: if set, the clock is gated when the bit is cleared 121 * @delay_us: delay in microseconds after which the clock is considered stable 122 */ 123 struct ingenic_cgu_gate_info { 124 unsigned reg; 125 u8 bit; 126 bool clear_to_gate; 127 u16 delay_us; 128 }; 129 130 /** 131 * struct ingenic_cgu_custom_info - information about a custom (SoC) clock 132 * @clk_ops: custom clock operation callbacks 133 */ 134 struct ingenic_cgu_custom_info { 135 const struct clk_ops *clk_ops; 136 }; 137 138 /** 139 * struct ingenic_cgu_clk_info - information about a clock 140 * @name: name of the clock 141 * @type: a bitmask formed from CGU_CLK_* values 142 * @flags: common clock flags to set on this clock 143 * @parents: an array of the indices of potential parents of this clock 144 * within the clock_info array of the CGU, or -1 in entries 145 * which correspond to no valid parent 146 * @pll: information valid if type includes CGU_CLK_PLL 147 * @gate: information valid if type includes CGU_CLK_GATE 148 * @mux: information valid if type includes CGU_CLK_MUX 149 * @div: information valid if type includes CGU_CLK_DIV 150 * @fixdiv: information valid if type includes CGU_CLK_FIXDIV 151 * @custom: information valid if type includes CGU_CLK_CUSTOM 152 */ 153 struct ingenic_cgu_clk_info { 154 const char *name; 155 156 enum { 157 CGU_CLK_NONE = 0, 158 CGU_CLK_EXT = BIT(0), 159 CGU_CLK_PLL = BIT(1), 160 CGU_CLK_GATE = BIT(2), 161 CGU_CLK_MUX = BIT(3), 162 CGU_CLK_MUX_GLITCHFREE = BIT(4), 163 CGU_CLK_DIV = BIT(5), 164 CGU_CLK_FIXDIV = BIT(6), 165 CGU_CLK_CUSTOM = BIT(7), 166 } type; 167 168 unsigned long flags; 169 170 int parents[4]; 171 172 union { 173 struct ingenic_cgu_pll_info pll; 174 175 struct { 176 struct ingenic_cgu_gate_info gate; 177 struct ingenic_cgu_mux_info mux; 178 struct ingenic_cgu_div_info div; 179 struct ingenic_cgu_fixdiv_info fixdiv; 180 }; 181 182 struct ingenic_cgu_custom_info custom; 183 }; 184 }; 185 186 /** 187 * struct ingenic_cgu - data about the CGU 188 * @np: the device tree node that caused the CGU to be probed 189 * @base: the ioremap'ed base address of the CGU registers 190 * @clock_info: an array containing information about implemented clocks 191 * @clocks: used to provide clocks to DT, allows lookup of struct clk* 192 * @lock: lock to be held whilst manipulating CGU registers 193 */ 194 struct ingenic_cgu { 195 struct device_node *np; 196 void __iomem *base; 197 198 const struct ingenic_cgu_clk_info *clock_info; 199 struct clk_onecell_data clocks; 200 201 spinlock_t lock; 202 }; 203 204 /** 205 * struct ingenic_clk - private data for a clock 206 * @hw: see Documentation/driver-api/clk.rst 207 * @cgu: a pointer to the CGU data 208 * @idx: the index of this clock in cgu->clock_info 209 */ 210 struct ingenic_clk { 211 struct clk_hw hw; 212 struct ingenic_cgu *cgu; 213 unsigned idx; 214 }; 215 216 #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) 217 218 /** 219 * ingenic_cgu_new() - create a new CGU instance 220 * @clock_info: an array of clock information structures describing the clocks 221 * which are implemented by the CGU 222 * @num_clocks: the number of entries in clock_info 223 * @np: the device tree node which causes this CGU to be probed 224 * 225 * Return: a pointer to the CGU instance if initialisation is successful, 226 * otherwise NULL. 227 */ 228 struct ingenic_cgu * 229 ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, 230 unsigned num_clocks, struct device_node *np); 231 232 /** 233 * ingenic_cgu_register_clocks() - Registers the clocks 234 * @cgu: pointer to cgu data 235 * 236 * Register the clocks described by the CGU with the common clock framework. 237 * 238 * Return: 0 on success or -errno if unsuccesful. 239 */ 240 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); 241 242 #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */ 243