1 /* 2 * Ingenic SoC CGU driver 3 * 4 * Copyright (c) 2013-2015 Imagination Technologies 5 * Author: Paul Burton <paul.burton@imgtec.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #ifndef __DRIVERS_CLK_INGENIC_CGU_H__ 19 #define __DRIVERS_CLK_INGENIC_CGU_H__ 20 21 #include <linux/bitops.h> 22 #include <linux/of.h> 23 #include <linux/spinlock.h> 24 25 /** 26 * struct ingenic_cgu_pll_info - information about a PLL 27 * @reg: the offset of the PLL's control register within the CGU 28 * @m_shift: the number of bits to shift the multiplier value by (ie. the 29 * index of the lowest bit of the multiplier value in the PLL's 30 * control register) 31 * @m_bits: the size of the multiplier field in bits 32 * @m_offset: the multiplier value which encodes to 0 in the PLL's control 33 * register 34 * @n_shift: the number of bits to shift the divider value by (ie. the 35 * index of the lowest bit of the divider value in the PLL's 36 * control register) 37 * @n_bits: the size of the divider field in bits 38 * @n_offset: the divider value which encodes to 0 in the PLL's control 39 * register 40 * @od_shift: the number of bits to shift the post-VCO divider value by (ie. 41 * the index of the lowest bit of the post-VCO divider value in 42 * the PLL's control register) 43 * @od_bits: the size of the post-VCO divider field in bits 44 * @od_max: the maximum post-VCO divider value 45 * @od_encoding: a pointer to an array mapping post-VCO divider values to 46 * their encoded values in the PLL control register, or -1 for 47 * unsupported values 48 * @bypass_bit: the index of the bypass bit in the PLL control register 49 * @enable_bit: the index of the enable bit in the PLL control register 50 * @stable_bit: the index of the stable bit in the PLL control register 51 */ 52 struct ingenic_cgu_pll_info { 53 unsigned reg; 54 const s8 *od_encoding; 55 u8 m_shift, m_bits, m_offset; 56 u8 n_shift, n_bits, n_offset; 57 u8 od_shift, od_bits, od_max; 58 u8 bypass_bit; 59 u8 enable_bit; 60 u8 stable_bit; 61 }; 62 63 /** 64 * struct ingenic_cgu_mux_info - information about a clock mux 65 * @reg: offset of the mux control register within the CGU 66 * @shift: number of bits to shift the mux value by (ie. the index of 67 * the lowest bit of the mux value within its control register) 68 * @bits: the size of the mux value in bits 69 */ 70 struct ingenic_cgu_mux_info { 71 unsigned reg; 72 u8 shift; 73 u8 bits; 74 }; 75 76 /** 77 * struct ingenic_cgu_div_info - information about a divider 78 * @reg: offset of the divider control register within the CGU 79 * @shift: number of bits to shift the divide value by (ie. the index of 80 * the lowest bit of the divide value within its control register) 81 * @bits: the size of the divide value in bits 82 * @ce_bit: the index of the change enable bit within reg, or -1 if there 83 * isn't one 84 * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one 85 * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one 86 */ 87 struct ingenic_cgu_div_info { 88 unsigned reg; 89 u8 shift; 90 u8 bits; 91 s8 ce_bit; 92 s8 busy_bit; 93 s8 stop_bit; 94 }; 95 96 /** 97 * struct ingenic_cgu_fixdiv_info - information about a fixed divider 98 * @div: the divider applied to the parent clock 99 */ 100 struct ingenic_cgu_fixdiv_info { 101 unsigned div; 102 }; 103 104 /** 105 * struct ingenic_cgu_gate_info - information about a clock gate 106 * @reg: offset of the gate control register within the CGU 107 * @bit: offset of the bit in the register that controls the gate 108 */ 109 struct ingenic_cgu_gate_info { 110 unsigned reg; 111 u8 bit; 112 }; 113 114 /** 115 * struct ingenic_cgu_custom_info - information about a custom (SoC) clock 116 * @clk_ops: custom clock operation callbacks 117 */ 118 struct ingenic_cgu_custom_info { 119 struct clk_ops *clk_ops; 120 }; 121 122 /** 123 * struct ingenic_cgu_clk_info - information about a clock 124 * @name: name of the clock 125 * @type: a bitmask formed from CGU_CLK_* values 126 * @parents: an array of the indices of potential parents of this clock 127 * within the clock_info array of the CGU, or -1 in entries 128 * which correspond to no valid parent 129 * @pll: information valid if type includes CGU_CLK_PLL 130 * @gate: information valid if type includes CGU_CLK_GATE 131 * @mux: information valid if type includes CGU_CLK_MUX 132 * @div: information valid if type includes CGU_CLK_DIV 133 * @fixdiv: information valid if type includes CGU_CLK_FIXDIV 134 * @custom: information valid if type includes CGU_CLK_CUSTOM 135 */ 136 struct ingenic_cgu_clk_info { 137 const char *name; 138 139 enum { 140 CGU_CLK_NONE = 0, 141 CGU_CLK_EXT = BIT(0), 142 CGU_CLK_PLL = BIT(1), 143 CGU_CLK_GATE = BIT(2), 144 CGU_CLK_MUX = BIT(3), 145 CGU_CLK_MUX_GLITCHFREE = BIT(4), 146 CGU_CLK_DIV = BIT(5), 147 CGU_CLK_FIXDIV = BIT(6), 148 CGU_CLK_CUSTOM = BIT(7), 149 } type; 150 151 int parents[4]; 152 153 union { 154 struct ingenic_cgu_pll_info pll; 155 156 struct { 157 struct ingenic_cgu_gate_info gate; 158 struct ingenic_cgu_mux_info mux; 159 struct ingenic_cgu_div_info div; 160 struct ingenic_cgu_fixdiv_info fixdiv; 161 }; 162 163 struct ingenic_cgu_custom_info custom; 164 }; 165 }; 166 167 /** 168 * struct ingenic_cgu - data about the CGU 169 * @np: the device tree node that caused the CGU to be probed 170 * @base: the ioremap'ed base address of the CGU registers 171 * @clock_info: an array containing information about implemented clocks 172 * @clocks: used to provide clocks to DT, allows lookup of struct clk* 173 * @lock: lock to be held whilst manipulating CGU registers 174 */ 175 struct ingenic_cgu { 176 struct device_node *np; 177 void __iomem *base; 178 179 const struct ingenic_cgu_clk_info *clock_info; 180 struct clk_onecell_data clocks; 181 182 spinlock_t lock; 183 }; 184 185 /** 186 * struct ingenic_clk - private data for a clock 187 * @hw: see Documentation/clk.txt 188 * @cgu: a pointer to the CGU data 189 * @idx: the index of this clock in cgu->clock_info 190 */ 191 struct ingenic_clk { 192 struct clk_hw hw; 193 struct ingenic_cgu *cgu; 194 unsigned idx; 195 }; 196 197 #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) 198 199 /** 200 * ingenic_cgu_new() - create a new CGU instance 201 * @clock_info: an array of clock information structures describing the clocks 202 * which are implemented by the CGU 203 * @num_clocks: the number of entries in clock_info 204 * @np: the device tree node which causes this CGU to be probed 205 * 206 * Return: a pointer to the CGU instance if initialisation is successful, 207 * otherwise NULL. 208 */ 209 struct ingenic_cgu * 210 ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, 211 unsigned num_clocks, struct device_node *np); 212 213 /** 214 * ingenic_cgu_register_clocks() - Registers the clocks 215 * @cgu: pointer to cgu data 216 * 217 * Register the clocks described by the CGU with the common clock framework. 218 * 219 * Return: 0 on success or -errno if unsuccesful. 220 */ 221 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); 222 223 #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */ 224