1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Ingenic SoC CGU driver 4 * 5 * Copyright (c) 2013-2015 Imagination Technologies 6 * Author: Paul Burton <paul.burton@mips.com> 7 */ 8 9 #ifndef __DRIVERS_CLK_INGENIC_CGU_H__ 10 #define __DRIVERS_CLK_INGENIC_CGU_H__ 11 12 #include <linux/bitops.h> 13 #include <linux/clk-provider.h> 14 #include <linux/of.h> 15 #include <linux/spinlock.h> 16 17 /** 18 * struct ingenic_cgu_pll_info - information about a PLL 19 * @reg: the offset of the PLL's control register within the CGU 20 * @rate_multiplier: the multiplier needed by pll rate calculation 21 * @m_shift: the number of bits to shift the multiplier value by (ie. the 22 * index of the lowest bit of the multiplier value in the PLL's 23 * control register) 24 * @m_bits: the size of the multiplier field in bits 25 * @m_offset: the multiplier value which encodes to 0 in the PLL's control 26 * register 27 * @n_shift: the number of bits to shift the divider value by (ie. the 28 * index of the lowest bit of the divider value in the PLL's 29 * control register) 30 * @n_bits: the size of the divider field in bits 31 * @n_offset: the divider value which encodes to 0 in the PLL's control 32 * register 33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie. 34 * the index of the lowest bit of the post-VCO divider value in 35 * the PLL's control register) 36 * @od_bits: the size of the post-VCO divider field in bits, or 0 if no 37 * OD field exists (then the OD is fixed to 1) 38 * @od_max: the maximum post-VCO divider value 39 * @od_encoding: a pointer to an array mapping post-VCO divider values to 40 * their encoded values in the PLL control register, or -1 for 41 * unsupported values 42 * @bypass_reg: the offset of the bypass control register within the CGU 43 * @bypass_bit: the index of the bypass bit in the PLL control register, or 44 * -1 if there is no bypass bit 45 * @enable_bit: the index of the enable bit in the PLL control register 46 * @stable_bit: the index of the stable bit in the PLL control register 47 */ 48 struct ingenic_cgu_pll_info { 49 unsigned reg; 50 unsigned rate_multiplier; 51 const s8 *od_encoding; 52 u8 m_shift, m_bits, m_offset; 53 u8 n_shift, n_bits, n_offset; 54 u8 od_shift, od_bits, od_max; 55 unsigned bypass_reg; 56 s8 bypass_bit; 57 u8 enable_bit; 58 u8 stable_bit; 59 void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, 60 unsigned long rate, unsigned long parent_rate, 61 unsigned int *m, unsigned int *n, unsigned int *od); 62 }; 63 64 /** 65 * struct ingenic_cgu_mux_info - information about a clock mux 66 * @reg: offset of the mux control register within the CGU 67 * @shift: number of bits to shift the mux value by (ie. the index of 68 * the lowest bit of the mux value within its control register) 69 * @bits: the size of the mux value in bits 70 */ 71 struct ingenic_cgu_mux_info { 72 unsigned reg; 73 u8 shift; 74 u8 bits; 75 }; 76 77 /** 78 * struct ingenic_cgu_div_info - information about a divider 79 * @reg: offset of the divider control register within the CGU 80 * @shift: number of bits to left shift the divide value by (ie. the index of 81 * the lowest bit of the divide value within its control register) 82 * @div: number to divide the divider value by (i.e. if the 83 * effective divider value is the value written to the register 84 * multiplied by some constant) 85 * @bits: the size of the divide value in bits 86 * @ce_bit: the index of the change enable bit within reg, or -1 if there 87 * isn't one 88 * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one 89 * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one 90 * @bypass_mask: mask of parent clocks for which the divider does not apply 91 * @div_table: optional table to map the value read from the register to the 92 * actual divider value 93 */ 94 struct ingenic_cgu_div_info { 95 unsigned reg; 96 u8 shift; 97 u8 div; 98 u8 bits; 99 s8 ce_bit; 100 s8 busy_bit; 101 s8 stop_bit; 102 u8 bypass_mask; 103 const u8 *div_table; 104 }; 105 106 /** 107 * struct ingenic_cgu_fixdiv_info - information about a fixed divider 108 * @div: the divider applied to the parent clock 109 */ 110 struct ingenic_cgu_fixdiv_info { 111 unsigned div; 112 }; 113 114 /** 115 * struct ingenic_cgu_gate_info - information about a clock gate 116 * @reg: offset of the gate control register within the CGU 117 * @bit: offset of the bit in the register that controls the gate 118 * @clear_to_gate: if set, the clock is gated when the bit is cleared 119 * @delay_us: delay in microseconds after which the clock is considered stable 120 */ 121 struct ingenic_cgu_gate_info { 122 unsigned reg; 123 u8 bit; 124 bool clear_to_gate; 125 u16 delay_us; 126 }; 127 128 /** 129 * struct ingenic_cgu_custom_info - information about a custom (SoC) clock 130 * @clk_ops: custom clock operation callbacks 131 */ 132 struct ingenic_cgu_custom_info { 133 const struct clk_ops *clk_ops; 134 }; 135 136 /** 137 * struct ingenic_cgu_clk_info - information about a clock 138 * @name: name of the clock 139 * @type: a bitmask formed from CGU_CLK_* values 140 * @flags: common clock flags to set on this clock 141 * @parents: an array of the indices of potential parents of this clock 142 * within the clock_info array of the CGU, or -1 in entries 143 * which correspond to no valid parent 144 * @pll: information valid if type includes CGU_CLK_PLL 145 * @gate: information valid if type includes CGU_CLK_GATE 146 * @mux: information valid if type includes CGU_CLK_MUX 147 * @div: information valid if type includes CGU_CLK_DIV 148 * @fixdiv: information valid if type includes CGU_CLK_FIXDIV 149 * @custom: information valid if type includes CGU_CLK_CUSTOM 150 */ 151 struct ingenic_cgu_clk_info { 152 const char *name; 153 154 enum { 155 CGU_CLK_NONE = 0, 156 CGU_CLK_EXT = BIT(0), 157 CGU_CLK_PLL = BIT(1), 158 CGU_CLK_GATE = BIT(2), 159 CGU_CLK_MUX = BIT(3), 160 CGU_CLK_MUX_GLITCHFREE = BIT(4), 161 CGU_CLK_DIV = BIT(5), 162 CGU_CLK_FIXDIV = BIT(6), 163 CGU_CLK_CUSTOM = BIT(7), 164 } type; 165 166 unsigned long flags; 167 168 int parents[4]; 169 170 union { 171 struct ingenic_cgu_pll_info pll; 172 173 struct { 174 struct ingenic_cgu_gate_info gate; 175 struct ingenic_cgu_mux_info mux; 176 struct ingenic_cgu_div_info div; 177 struct ingenic_cgu_fixdiv_info fixdiv; 178 }; 179 180 struct ingenic_cgu_custom_info custom; 181 }; 182 }; 183 184 /** 185 * struct ingenic_cgu - data about the CGU 186 * @np: the device tree node that caused the CGU to be probed 187 * @base: the ioremap'ed base address of the CGU registers 188 * @clock_info: an array containing information about implemented clocks 189 * @clocks: used to provide clocks to DT, allows lookup of struct clk* 190 * @lock: lock to be held whilst manipulating CGU registers 191 */ 192 struct ingenic_cgu { 193 struct device_node *np; 194 void __iomem *base; 195 196 const struct ingenic_cgu_clk_info *clock_info; 197 struct clk_onecell_data clocks; 198 199 spinlock_t lock; 200 }; 201 202 /** 203 * struct ingenic_clk - private data for a clock 204 * @hw: see Documentation/driver-api/clk.rst 205 * @cgu: a pointer to the CGU data 206 * @idx: the index of this clock in cgu->clock_info 207 */ 208 struct ingenic_clk { 209 struct clk_hw hw; 210 struct ingenic_cgu *cgu; 211 unsigned idx; 212 }; 213 214 #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) 215 216 /** 217 * ingenic_cgu_new() - create a new CGU instance 218 * @clock_info: an array of clock information structures describing the clocks 219 * which are implemented by the CGU 220 * @num_clocks: the number of entries in clock_info 221 * @np: the device tree node which causes this CGU to be probed 222 * 223 * Return: a pointer to the CGU instance if initialisation is successful, 224 * otherwise NULL. 225 */ 226 struct ingenic_cgu * 227 ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, 228 unsigned num_clocks, struct device_node *np); 229 230 /** 231 * ingenic_cgu_register_clocks() - Registers the clocks 232 * @cgu: pointer to cgu data 233 * 234 * Register the clocks described by the CGU with the common clock framework. 235 * 236 * Return: 0 on success or -errno if unsuccesful. 237 */ 238 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); 239 240 #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */ 241