1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Ingenic SoC CGU driver 4 * 5 * Copyright (c) 2013-2015 Imagination Technologies 6 * Author: Paul Burton <paul.burton@mips.com> 7 */ 8 9 #ifndef __DRIVERS_CLK_INGENIC_CGU_H__ 10 #define __DRIVERS_CLK_INGENIC_CGU_H__ 11 12 #include <linux/bitops.h> 13 #include <linux/clk-provider.h> 14 #include <linux/of.h> 15 #include <linux/spinlock.h> 16 17 /** 18 * struct ingenic_cgu_pll_info - information about a PLL 19 * @reg: the offset of the PLL's control register within the CGU 20 * @m_shift: the number of bits to shift the multiplier value by (ie. the 21 * index of the lowest bit of the multiplier value in the PLL's 22 * control register) 23 * @m_bits: the size of the multiplier field in bits 24 * @m_offset: the multiplier value which encodes to 0 in the PLL's control 25 * register 26 * @n_shift: the number of bits to shift the divider value by (ie. the 27 * index of the lowest bit of the divider value in the PLL's 28 * control register) 29 * @n_bits: the size of the divider field in bits 30 * @n_offset: the divider value which encodes to 0 in the PLL's control 31 * register 32 * @od_shift: the number of bits to shift the post-VCO divider value by (ie. 33 * the index of the lowest bit of the post-VCO divider value in 34 * the PLL's control register) 35 * @od_bits: the size of the post-VCO divider field in bits 36 * @od_max: the maximum post-VCO divider value 37 * @od_encoding: a pointer to an array mapping post-VCO divider values to 38 * their encoded values in the PLL control register, or -1 for 39 * unsupported values 40 * @bypass_bit: the index of the bypass bit in the PLL control register 41 * @enable_bit: the index of the enable bit in the PLL control register 42 * @stable_bit: the index of the stable bit in the PLL control register 43 * @no_bypass_bit: if set, the PLL has no bypass functionality 44 */ 45 struct ingenic_cgu_pll_info { 46 unsigned reg; 47 const s8 *od_encoding; 48 u8 m_shift, m_bits, m_offset; 49 u8 n_shift, n_bits, n_offset; 50 u8 od_shift, od_bits, od_max; 51 u8 bypass_bit; 52 u8 enable_bit; 53 u8 stable_bit; 54 bool no_bypass_bit; 55 }; 56 57 /** 58 * struct ingenic_cgu_mux_info - information about a clock mux 59 * @reg: offset of the mux control register within the CGU 60 * @shift: number of bits to shift the mux value by (ie. the index of 61 * the lowest bit of the mux value within its control register) 62 * @bits: the size of the mux value in bits 63 */ 64 struct ingenic_cgu_mux_info { 65 unsigned reg; 66 u8 shift; 67 u8 bits; 68 }; 69 70 /** 71 * struct ingenic_cgu_div_info - information about a divider 72 * @reg: offset of the divider control register within the CGU 73 * @shift: number of bits to left shift the divide value by (ie. the index of 74 * the lowest bit of the divide value within its control register) 75 * @div: number to divide the divider value by (i.e. if the 76 * effective divider value is the value written to the register 77 * multiplied by some constant) 78 * @bits: the size of the divide value in bits 79 * @ce_bit: the index of the change enable bit within reg, or -1 if there 80 * isn't one 81 * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one 82 * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one 83 * @div_table: optional table to map the value read from the register to the 84 * actual divider value 85 */ 86 struct ingenic_cgu_div_info { 87 unsigned reg; 88 u8 shift; 89 u8 div; 90 u8 bits; 91 s8 ce_bit; 92 s8 busy_bit; 93 s8 stop_bit; 94 const u8 *div_table; 95 }; 96 97 /** 98 * struct ingenic_cgu_fixdiv_info - information about a fixed divider 99 * @div: the divider applied to the parent clock 100 */ 101 struct ingenic_cgu_fixdiv_info { 102 unsigned div; 103 }; 104 105 /** 106 * struct ingenic_cgu_gate_info - information about a clock gate 107 * @reg: offset of the gate control register within the CGU 108 * @bit: offset of the bit in the register that controls the gate 109 * @clear_to_gate: if set, the clock is gated when the bit is cleared 110 * @delay_us: delay in microseconds after which the clock is considered stable 111 */ 112 struct ingenic_cgu_gate_info { 113 unsigned reg; 114 u8 bit; 115 bool clear_to_gate; 116 u16 delay_us; 117 }; 118 119 /** 120 * struct ingenic_cgu_custom_info - information about a custom (SoC) clock 121 * @clk_ops: custom clock operation callbacks 122 */ 123 struct ingenic_cgu_custom_info { 124 const struct clk_ops *clk_ops; 125 }; 126 127 /** 128 * struct ingenic_cgu_clk_info - information about a clock 129 * @name: name of the clock 130 * @type: a bitmask formed from CGU_CLK_* values 131 * @parents: an array of the indices of potential parents of this clock 132 * within the clock_info array of the CGU, or -1 in entries 133 * which correspond to no valid parent 134 * @pll: information valid if type includes CGU_CLK_PLL 135 * @gate: information valid if type includes CGU_CLK_GATE 136 * @mux: information valid if type includes CGU_CLK_MUX 137 * @div: information valid if type includes CGU_CLK_DIV 138 * @fixdiv: information valid if type includes CGU_CLK_FIXDIV 139 * @custom: information valid if type includes CGU_CLK_CUSTOM 140 */ 141 struct ingenic_cgu_clk_info { 142 const char *name; 143 144 enum { 145 CGU_CLK_NONE = 0, 146 CGU_CLK_EXT = BIT(0), 147 CGU_CLK_PLL = BIT(1), 148 CGU_CLK_GATE = BIT(2), 149 CGU_CLK_MUX = BIT(3), 150 CGU_CLK_MUX_GLITCHFREE = BIT(4), 151 CGU_CLK_DIV = BIT(5), 152 CGU_CLK_FIXDIV = BIT(6), 153 CGU_CLK_CUSTOM = BIT(7), 154 } type; 155 156 int parents[4]; 157 158 union { 159 struct ingenic_cgu_pll_info pll; 160 161 struct { 162 struct ingenic_cgu_gate_info gate; 163 struct ingenic_cgu_mux_info mux; 164 struct ingenic_cgu_div_info div; 165 struct ingenic_cgu_fixdiv_info fixdiv; 166 }; 167 168 struct ingenic_cgu_custom_info custom; 169 }; 170 }; 171 172 /** 173 * struct ingenic_cgu - data about the CGU 174 * @np: the device tree node that caused the CGU to be probed 175 * @base: the ioremap'ed base address of the CGU registers 176 * @clock_info: an array containing information about implemented clocks 177 * @clocks: used to provide clocks to DT, allows lookup of struct clk* 178 * @lock: lock to be held whilst manipulating CGU registers 179 */ 180 struct ingenic_cgu { 181 struct device_node *np; 182 void __iomem *base; 183 184 const struct ingenic_cgu_clk_info *clock_info; 185 struct clk_onecell_data clocks; 186 187 spinlock_t lock; 188 }; 189 190 /** 191 * struct ingenic_clk - private data for a clock 192 * @hw: see Documentation/driver-api/clk.rst 193 * @cgu: a pointer to the CGU data 194 * @idx: the index of this clock in cgu->clock_info 195 */ 196 struct ingenic_clk { 197 struct clk_hw hw; 198 struct ingenic_cgu *cgu; 199 unsigned idx; 200 }; 201 202 #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) 203 204 /** 205 * ingenic_cgu_new() - create a new CGU instance 206 * @clock_info: an array of clock information structures describing the clocks 207 * which are implemented by the CGU 208 * @num_clocks: the number of entries in clock_info 209 * @np: the device tree node which causes this CGU to be probed 210 * 211 * Return: a pointer to the CGU instance if initialisation is successful, 212 * otherwise NULL. 213 */ 214 struct ingenic_cgu * 215 ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, 216 unsigned num_clocks, struct device_node *np); 217 218 /** 219 * ingenic_cgu_register_clocks() - Registers the clocks 220 * @cgu: pointer to cgu data 221 * 222 * Register the clocks described by the CGU with the common clock framework. 223 * 224 * Return: 0 on success or -errno if unsuccesful. 225 */ 226 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); 227 228 #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */ 229