1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Ingenic SoC CGU driver 4 * 5 * Copyright (c) 2013-2015 Imagination Technologies 6 * Author: Paul Burton <paul.burton@mips.com> 7 */ 8 9 #ifndef __DRIVERS_CLK_INGENIC_CGU_H__ 10 #define __DRIVERS_CLK_INGENIC_CGU_H__ 11 12 #include <linux/bitops.h> 13 #include <linux/clk-provider.h> 14 #include <linux/of.h> 15 #include <linux/spinlock.h> 16 17 /** 18 * struct ingenic_cgu_pll_info - information about a PLL 19 * @reg: the offset of the PLL's control register within the CGU 20 * @rate_multiplier: the multiplier needed by pll rate calculation 21 * @m_shift: the number of bits to shift the multiplier value by (ie. the 22 * index of the lowest bit of the multiplier value in the PLL's 23 * control register) 24 * @m_bits: the size of the multiplier field in bits 25 * @m_offset: the multiplier value which encodes to 0 in the PLL's control 26 * register 27 * @n_shift: the number of bits to shift the divider value by (ie. the 28 * index of the lowest bit of the divider value in the PLL's 29 * control register) 30 * @n_bits: the size of the divider field in bits 31 * @n_offset: the divider value which encodes to 0 in the PLL's control 32 * register 33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie. 34 * the index of the lowest bit of the post-VCO divider value in 35 * the PLL's control register) 36 * @od_bits: the size of the post-VCO divider field in bits 37 * @od_max: the maximum post-VCO divider value 38 * @od_encoding: a pointer to an array mapping post-VCO divider values to 39 * their encoded values in the PLL control register, or -1 for 40 * unsupported values 41 * @bypass_reg: the offset of the bypass control register within the CGU 42 * @bypass_bit: the index of the bypass bit in the PLL control register, or 43 * -1 if there is no bypass bit 44 * @enable_bit: the index of the enable bit in the PLL control register 45 * @stable_bit: the index of the stable bit in the PLL control register 46 */ 47 struct ingenic_cgu_pll_info { 48 unsigned reg; 49 unsigned rate_multiplier; 50 const s8 *od_encoding; 51 u8 m_shift, m_bits, m_offset; 52 u8 n_shift, n_bits, n_offset; 53 u8 od_shift, od_bits, od_max; 54 unsigned bypass_reg; 55 s8 bypass_bit; 56 u8 enable_bit; 57 u8 stable_bit; 58 void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, 59 unsigned long rate, unsigned long parent_rate, 60 unsigned int *m, unsigned int *n, unsigned int *od); 61 }; 62 63 /** 64 * struct ingenic_cgu_mux_info - information about a clock mux 65 * @reg: offset of the mux control register within the CGU 66 * @shift: number of bits to shift the mux value by (ie. the index of 67 * the lowest bit of the mux value within its control register) 68 * @bits: the size of the mux value in bits 69 */ 70 struct ingenic_cgu_mux_info { 71 unsigned reg; 72 u8 shift; 73 u8 bits; 74 }; 75 76 /** 77 * struct ingenic_cgu_div_info - information about a divider 78 * @reg: offset of the divider control register within the CGU 79 * @shift: number of bits to left shift the divide value by (ie. the index of 80 * the lowest bit of the divide value within its control register) 81 * @div: number to divide the divider value by (i.e. if the 82 * effective divider value is the value written to the register 83 * multiplied by some constant) 84 * @bits: the size of the divide value in bits 85 * @ce_bit: the index of the change enable bit within reg, or -1 if there 86 * isn't one 87 * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one 88 * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one 89 * @bypass_mask: mask of parent clocks for which the divider does not apply 90 * @div_table: optional table to map the value read from the register to the 91 * actual divider value 92 */ 93 struct ingenic_cgu_div_info { 94 unsigned reg; 95 u8 shift; 96 u8 div; 97 u8 bits; 98 s8 ce_bit; 99 s8 busy_bit; 100 s8 stop_bit; 101 u8 bypass_mask; 102 const u8 *div_table; 103 }; 104 105 /** 106 * struct ingenic_cgu_fixdiv_info - information about a fixed divider 107 * @div: the divider applied to the parent clock 108 */ 109 struct ingenic_cgu_fixdiv_info { 110 unsigned div; 111 }; 112 113 /** 114 * struct ingenic_cgu_gate_info - information about a clock gate 115 * @reg: offset of the gate control register within the CGU 116 * @bit: offset of the bit in the register that controls the gate 117 * @clear_to_gate: if set, the clock is gated when the bit is cleared 118 * @delay_us: delay in microseconds after which the clock is considered stable 119 */ 120 struct ingenic_cgu_gate_info { 121 unsigned reg; 122 u8 bit; 123 bool clear_to_gate; 124 u16 delay_us; 125 }; 126 127 /** 128 * struct ingenic_cgu_custom_info - information about a custom (SoC) clock 129 * @clk_ops: custom clock operation callbacks 130 */ 131 struct ingenic_cgu_custom_info { 132 const struct clk_ops *clk_ops; 133 }; 134 135 /** 136 * struct ingenic_cgu_clk_info - information about a clock 137 * @name: name of the clock 138 * @type: a bitmask formed from CGU_CLK_* values 139 * @flags: common clock flags to set on this clock 140 * @parents: an array of the indices of potential parents of this clock 141 * within the clock_info array of the CGU, or -1 in entries 142 * which correspond to no valid parent 143 * @pll: information valid if type includes CGU_CLK_PLL 144 * @gate: information valid if type includes CGU_CLK_GATE 145 * @mux: information valid if type includes CGU_CLK_MUX 146 * @div: information valid if type includes CGU_CLK_DIV 147 * @fixdiv: information valid if type includes CGU_CLK_FIXDIV 148 * @custom: information valid if type includes CGU_CLK_CUSTOM 149 */ 150 struct ingenic_cgu_clk_info { 151 const char *name; 152 153 enum { 154 CGU_CLK_NONE = 0, 155 CGU_CLK_EXT = BIT(0), 156 CGU_CLK_PLL = BIT(1), 157 CGU_CLK_GATE = BIT(2), 158 CGU_CLK_MUX = BIT(3), 159 CGU_CLK_MUX_GLITCHFREE = BIT(4), 160 CGU_CLK_DIV = BIT(5), 161 CGU_CLK_FIXDIV = BIT(6), 162 CGU_CLK_CUSTOM = BIT(7), 163 } type; 164 165 unsigned long flags; 166 167 int parents[4]; 168 169 union { 170 struct ingenic_cgu_pll_info pll; 171 172 struct { 173 struct ingenic_cgu_gate_info gate; 174 struct ingenic_cgu_mux_info mux; 175 struct ingenic_cgu_div_info div; 176 struct ingenic_cgu_fixdiv_info fixdiv; 177 }; 178 179 struct ingenic_cgu_custom_info custom; 180 }; 181 }; 182 183 /** 184 * struct ingenic_cgu - data about the CGU 185 * @np: the device tree node that caused the CGU to be probed 186 * @base: the ioremap'ed base address of the CGU registers 187 * @clock_info: an array containing information about implemented clocks 188 * @clocks: used to provide clocks to DT, allows lookup of struct clk* 189 * @lock: lock to be held whilst manipulating CGU registers 190 */ 191 struct ingenic_cgu { 192 struct device_node *np; 193 void __iomem *base; 194 195 const struct ingenic_cgu_clk_info *clock_info; 196 struct clk_onecell_data clocks; 197 198 spinlock_t lock; 199 }; 200 201 /** 202 * struct ingenic_clk - private data for a clock 203 * @hw: see Documentation/driver-api/clk.rst 204 * @cgu: a pointer to the CGU data 205 * @idx: the index of this clock in cgu->clock_info 206 */ 207 struct ingenic_clk { 208 struct clk_hw hw; 209 struct ingenic_cgu *cgu; 210 unsigned idx; 211 }; 212 213 #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) 214 215 /** 216 * ingenic_cgu_new() - create a new CGU instance 217 * @clock_info: an array of clock information structures describing the clocks 218 * which are implemented by the CGU 219 * @num_clocks: the number of entries in clock_info 220 * @np: the device tree node which causes this CGU to be probed 221 * 222 * Return: a pointer to the CGU instance if initialisation is successful, 223 * otherwise NULL. 224 */ 225 struct ingenic_cgu * 226 ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, 227 unsigned num_clocks, struct device_node *np); 228 229 /** 230 * ingenic_cgu_register_clocks() - Registers the clocks 231 * @cgu: pointer to cgu data 232 * 233 * Register the clocks described by the CGU with the common clock framework. 234 * 235 * Return: 0 on success or -errno if unsuccesful. 236 */ 237 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); 238 239 #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */ 240