1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Ingenic SoC CGU driver 4 * 5 * Copyright (c) 2013-2015 Imagination Technologies 6 * Author: Paul Burton <paul.burton@mips.com> 7 */ 8 9 #ifndef __DRIVERS_CLK_INGENIC_CGU_H__ 10 #define __DRIVERS_CLK_INGENIC_CGU_H__ 11 12 #include <linux/bitops.h> 13 #include <linux/clk-provider.h> 14 #include <linux/of.h> 15 #include <linux/spinlock.h> 16 17 /** 18 * struct ingenic_cgu_pll_info - information about a PLL 19 * @reg: the offset of the PLL's control register within the CGU 20 * @rate_multiplier: the multiplier needed by pll rate calculation 21 * @m_shift: the number of bits to shift the multiplier value by (ie. the 22 * index of the lowest bit of the multiplier value in the PLL's 23 * control register) 24 * @m_bits: the size of the multiplier field in bits 25 * @m_offset: the multiplier value which encodes to 0 in the PLL's control 26 * register 27 * @n_shift: the number of bits to shift the divider value by (ie. the 28 * index of the lowest bit of the divider value in the PLL's 29 * control register) 30 * @n_bits: the size of the divider field in bits 31 * @n_offset: the divider value which encodes to 0 in the PLL's control 32 * register 33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie. 34 * the index of the lowest bit of the post-VCO divider value in 35 * the PLL's control register) 36 * @od_bits: the size of the post-VCO divider field in bits 37 * @od_max: the maximum post-VCO divider value 38 * @od_encoding: a pointer to an array mapping post-VCO divider values to 39 * their encoded values in the PLL control register, or -1 for 40 * unsupported values 41 * @bypass_reg: the offset of the bypass control register within the CGU 42 * @bypass_bit: the index of the bypass bit in the PLL control register 43 * @enable_bit: the index of the enable bit in the PLL control register 44 * @stable_bit: the index of the stable bit in the PLL control register 45 * @no_bypass_bit: if set, the PLL has no bypass functionality 46 */ 47 struct ingenic_cgu_pll_info { 48 unsigned reg; 49 unsigned rate_multiplier; 50 const s8 *od_encoding; 51 u8 m_shift, m_bits, m_offset; 52 u8 n_shift, n_bits, n_offset; 53 u8 od_shift, od_bits, od_max; 54 unsigned bypass_reg; 55 u8 bypass_bit; 56 u8 enable_bit; 57 u8 stable_bit; 58 bool no_bypass_bit; 59 }; 60 61 /** 62 * struct ingenic_cgu_mux_info - information about a clock mux 63 * @reg: offset of the mux control register within the CGU 64 * @shift: number of bits to shift the mux value by (ie. the index of 65 * the lowest bit of the mux value within its control register) 66 * @bits: the size of the mux value in bits 67 */ 68 struct ingenic_cgu_mux_info { 69 unsigned reg; 70 u8 shift; 71 u8 bits; 72 }; 73 74 /** 75 * struct ingenic_cgu_div_info - information about a divider 76 * @reg: offset of the divider control register within the CGU 77 * @shift: number of bits to left shift the divide value by (ie. the index of 78 * the lowest bit of the divide value within its control register) 79 * @div: number to divide the divider value by (i.e. if the 80 * effective divider value is the value written to the register 81 * multiplied by some constant) 82 * @bits: the size of the divide value in bits 83 * @ce_bit: the index of the change enable bit within reg, or -1 if there 84 * isn't one 85 * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one 86 * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one 87 * @bypass_mask: mask of parent clocks for which the divider does not apply 88 * @div_table: optional table to map the value read from the register to the 89 * actual divider value 90 */ 91 struct ingenic_cgu_div_info { 92 unsigned reg; 93 u8 shift; 94 u8 div; 95 u8 bits; 96 s8 ce_bit; 97 s8 busy_bit; 98 s8 stop_bit; 99 u8 bypass_mask; 100 const u8 *div_table; 101 }; 102 103 /** 104 * struct ingenic_cgu_fixdiv_info - information about a fixed divider 105 * @div: the divider applied to the parent clock 106 */ 107 struct ingenic_cgu_fixdiv_info { 108 unsigned div; 109 }; 110 111 /** 112 * struct ingenic_cgu_gate_info - information about a clock gate 113 * @reg: offset of the gate control register within the CGU 114 * @bit: offset of the bit in the register that controls the gate 115 * @clear_to_gate: if set, the clock is gated when the bit is cleared 116 * @delay_us: delay in microseconds after which the clock is considered stable 117 */ 118 struct ingenic_cgu_gate_info { 119 unsigned reg; 120 u8 bit; 121 bool clear_to_gate; 122 u16 delay_us; 123 }; 124 125 /** 126 * struct ingenic_cgu_custom_info - information about a custom (SoC) clock 127 * @clk_ops: custom clock operation callbacks 128 */ 129 struct ingenic_cgu_custom_info { 130 const struct clk_ops *clk_ops; 131 }; 132 133 /** 134 * struct ingenic_cgu_clk_info - information about a clock 135 * @name: name of the clock 136 * @type: a bitmask formed from CGU_CLK_* values 137 * @parents: an array of the indices of potential parents of this clock 138 * within the clock_info array of the CGU, or -1 in entries 139 * which correspond to no valid parent 140 * @pll: information valid if type includes CGU_CLK_PLL 141 * @gate: information valid if type includes CGU_CLK_GATE 142 * @mux: information valid if type includes CGU_CLK_MUX 143 * @div: information valid if type includes CGU_CLK_DIV 144 * @fixdiv: information valid if type includes CGU_CLK_FIXDIV 145 * @custom: information valid if type includes CGU_CLK_CUSTOM 146 */ 147 struct ingenic_cgu_clk_info { 148 const char *name; 149 150 enum { 151 CGU_CLK_NONE = 0, 152 CGU_CLK_EXT = BIT(0), 153 CGU_CLK_PLL = BIT(1), 154 CGU_CLK_GATE = BIT(2), 155 CGU_CLK_MUX = BIT(3), 156 CGU_CLK_MUX_GLITCHFREE = BIT(4), 157 CGU_CLK_DIV = BIT(5), 158 CGU_CLK_FIXDIV = BIT(6), 159 CGU_CLK_CUSTOM = BIT(7), 160 } type; 161 162 int parents[4]; 163 164 union { 165 struct ingenic_cgu_pll_info pll; 166 167 struct { 168 struct ingenic_cgu_gate_info gate; 169 struct ingenic_cgu_mux_info mux; 170 struct ingenic_cgu_div_info div; 171 struct ingenic_cgu_fixdiv_info fixdiv; 172 }; 173 174 struct ingenic_cgu_custom_info custom; 175 }; 176 }; 177 178 /** 179 * struct ingenic_cgu - data about the CGU 180 * @np: the device tree node that caused the CGU to be probed 181 * @base: the ioremap'ed base address of the CGU registers 182 * @clock_info: an array containing information about implemented clocks 183 * @clocks: used to provide clocks to DT, allows lookup of struct clk* 184 * @lock: lock to be held whilst manipulating CGU registers 185 */ 186 struct ingenic_cgu { 187 struct device_node *np; 188 void __iomem *base; 189 190 const struct ingenic_cgu_clk_info *clock_info; 191 struct clk_onecell_data clocks; 192 193 spinlock_t lock; 194 }; 195 196 /** 197 * struct ingenic_clk - private data for a clock 198 * @hw: see Documentation/driver-api/clk.rst 199 * @cgu: a pointer to the CGU data 200 * @idx: the index of this clock in cgu->clock_info 201 */ 202 struct ingenic_clk { 203 struct clk_hw hw; 204 struct ingenic_cgu *cgu; 205 unsigned idx; 206 }; 207 208 #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) 209 210 /** 211 * ingenic_cgu_new() - create a new CGU instance 212 * @clock_info: an array of clock information structures describing the clocks 213 * which are implemented by the CGU 214 * @num_clocks: the number of entries in clock_info 215 * @np: the device tree node which causes this CGU to be probed 216 * 217 * Return: a pointer to the CGU instance if initialisation is successful, 218 * otherwise NULL. 219 */ 220 struct ingenic_cgu * 221 ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, 222 unsigned num_clocks, struct device_node *np); 223 224 /** 225 * ingenic_cgu_register_clocks() - Registers the clocks 226 * @cgu: pointer to cgu data 227 * 228 * Register the clocks described by the CGU with the common clock framework. 229 * 230 * Return: 0 on success or -errno if unsuccesful. 231 */ 232 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); 233 234 #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */ 235