1c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2b066303fSPaul Burton /* 3b066303fSPaul Burton * Ingenic SoC CGU driver 4b066303fSPaul Burton * 5b066303fSPaul Burton * Copyright (c) 2013-2015 Imagination Technologies 6fb615d61SPaul Burton * Author: Paul Burton <paul.burton@mips.com> 7b066303fSPaul Burton */ 8b066303fSPaul Burton 9b066303fSPaul Burton #ifndef __DRIVERS_CLK_INGENIC_CGU_H__ 10b066303fSPaul Burton #define __DRIVERS_CLK_INGENIC_CGU_H__ 11b066303fSPaul Burton 12b066303fSPaul Burton #include <linux/bitops.h> 13b066303fSPaul Burton #include <linux/of.h> 14b066303fSPaul Burton #include <linux/spinlock.h> 15b066303fSPaul Burton 16b066303fSPaul Burton /** 17b066303fSPaul Burton * struct ingenic_cgu_pll_info - information about a PLL 18b066303fSPaul Burton * @reg: the offset of the PLL's control register within the CGU 19b066303fSPaul Burton * @m_shift: the number of bits to shift the multiplier value by (ie. the 20b066303fSPaul Burton * index of the lowest bit of the multiplier value in the PLL's 21b066303fSPaul Burton * control register) 22b066303fSPaul Burton * @m_bits: the size of the multiplier field in bits 23b066303fSPaul Burton * @m_offset: the multiplier value which encodes to 0 in the PLL's control 24b066303fSPaul Burton * register 25b066303fSPaul Burton * @n_shift: the number of bits to shift the divider value by (ie. the 26b066303fSPaul Burton * index of the lowest bit of the divider value in the PLL's 27b066303fSPaul Burton * control register) 28b066303fSPaul Burton * @n_bits: the size of the divider field in bits 29b066303fSPaul Burton * @n_offset: the divider value which encodes to 0 in the PLL's control 30b066303fSPaul Burton * register 31b066303fSPaul Burton * @od_shift: the number of bits to shift the post-VCO divider value by (ie. 32b066303fSPaul Burton * the index of the lowest bit of the post-VCO divider value in 33b066303fSPaul Burton * the PLL's control register) 34b066303fSPaul Burton * @od_bits: the size of the post-VCO divider field in bits 35b066303fSPaul Burton * @od_max: the maximum post-VCO divider value 36b066303fSPaul Burton * @od_encoding: a pointer to an array mapping post-VCO divider values to 37b066303fSPaul Burton * their encoded values in the PLL control register, or -1 for 38b066303fSPaul Burton * unsupported values 39b066303fSPaul Burton * @bypass_bit: the index of the bypass bit in the PLL control register 40b066303fSPaul Burton * @enable_bit: the index of the enable bit in the PLL control register 41b066303fSPaul Burton * @stable_bit: the index of the stable bit in the PLL control register 42268db077SPaul Cercueil * @no_bypass_bit: if set, the PLL has no bypass functionality 43b066303fSPaul Burton */ 44b066303fSPaul Burton struct ingenic_cgu_pll_info { 45b066303fSPaul Burton unsigned reg; 46b066303fSPaul Burton const s8 *od_encoding; 47b066303fSPaul Burton u8 m_shift, m_bits, m_offset; 48b066303fSPaul Burton u8 n_shift, n_bits, n_offset; 49b066303fSPaul Burton u8 od_shift, od_bits, od_max; 50b066303fSPaul Burton u8 bypass_bit; 51b066303fSPaul Burton u8 enable_bit; 52b066303fSPaul Burton u8 stable_bit; 53268db077SPaul Cercueil bool no_bypass_bit; 54b066303fSPaul Burton }; 55b066303fSPaul Burton 56b066303fSPaul Burton /** 57b066303fSPaul Burton * struct ingenic_cgu_mux_info - information about a clock mux 58b066303fSPaul Burton * @reg: offset of the mux control register within the CGU 59b066303fSPaul Burton * @shift: number of bits to shift the mux value by (ie. the index of 60b066303fSPaul Burton * the lowest bit of the mux value within its control register) 61b066303fSPaul Burton * @bits: the size of the mux value in bits 62b066303fSPaul Burton */ 63b066303fSPaul Burton struct ingenic_cgu_mux_info { 64b066303fSPaul Burton unsigned reg; 65b066303fSPaul Burton u8 shift; 66b066303fSPaul Burton u8 bits; 67b066303fSPaul Burton }; 68b066303fSPaul Burton 69b066303fSPaul Burton /** 70b066303fSPaul Burton * struct ingenic_cgu_div_info - information about a divider 71b066303fSPaul Burton * @reg: offset of the divider control register within the CGU 724afe2d1aSHarvey Hunt * @shift: number of bits to left shift the divide value by (ie. the index of 73b066303fSPaul Burton * the lowest bit of the divide value within its control register) 747ca4c922SPaul Cercueil * @div: number to divide the divider value by (i.e. if the 754afe2d1aSHarvey Hunt * effective divider value is the value written to the register 764afe2d1aSHarvey Hunt * multiplied by some constant) 77b066303fSPaul Burton * @bits: the size of the divide value in bits 78b066303fSPaul Burton * @ce_bit: the index of the change enable bit within reg, or -1 if there 79b066303fSPaul Burton * isn't one 80b066303fSPaul Burton * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one 81b066303fSPaul Burton * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one 82b066303fSPaul Burton */ 83b066303fSPaul Burton struct ingenic_cgu_div_info { 84b066303fSPaul Burton unsigned reg; 85b066303fSPaul Burton u8 shift; 864afe2d1aSHarvey Hunt u8 div; 87b066303fSPaul Burton u8 bits; 88b066303fSPaul Burton s8 ce_bit; 89b066303fSPaul Burton s8 busy_bit; 90b066303fSPaul Burton s8 stop_bit; 91b066303fSPaul Burton }; 92b066303fSPaul Burton 93b066303fSPaul Burton /** 94b066303fSPaul Burton * struct ingenic_cgu_fixdiv_info - information about a fixed divider 95b066303fSPaul Burton * @div: the divider applied to the parent clock 96b066303fSPaul Burton */ 97b066303fSPaul Burton struct ingenic_cgu_fixdiv_info { 98b066303fSPaul Burton unsigned div; 99b066303fSPaul Burton }; 100b066303fSPaul Burton 101b066303fSPaul Burton /** 102b066303fSPaul Burton * struct ingenic_cgu_gate_info - information about a clock gate 103b066303fSPaul Burton * @reg: offset of the gate control register within the CGU 104b066303fSPaul Burton * @bit: offset of the bit in the register that controls the gate 1057ef3844fSPaul Cercueil * @clear_to_gate: if set, the clock is gated when the bit is cleared 106261a831fSPaul Cercueil * @delay_us: delay in microseconds after which the clock is considered stable 107b066303fSPaul Burton */ 108b066303fSPaul Burton struct ingenic_cgu_gate_info { 109b066303fSPaul Burton unsigned reg; 110b066303fSPaul Burton u8 bit; 1117ef3844fSPaul Cercueil bool clear_to_gate; 112261a831fSPaul Cercueil u16 delay_us; 113b066303fSPaul Burton }; 114b066303fSPaul Burton 115b066303fSPaul Burton /** 116b066303fSPaul Burton * struct ingenic_cgu_custom_info - information about a custom (SoC) clock 117b066303fSPaul Burton * @clk_ops: custom clock operation callbacks 118b066303fSPaul Burton */ 119b066303fSPaul Burton struct ingenic_cgu_custom_info { 120ee1f9df2SPaul Cercueil const struct clk_ops *clk_ops; 121b066303fSPaul Burton }; 122b066303fSPaul Burton 123b066303fSPaul Burton /** 124b066303fSPaul Burton * struct ingenic_cgu_clk_info - information about a clock 125b066303fSPaul Burton * @name: name of the clock 126b066303fSPaul Burton * @type: a bitmask formed from CGU_CLK_* values 127b066303fSPaul Burton * @parents: an array of the indices of potential parents of this clock 128b066303fSPaul Burton * within the clock_info array of the CGU, or -1 in entries 129b066303fSPaul Burton * which correspond to no valid parent 130b066303fSPaul Burton * @pll: information valid if type includes CGU_CLK_PLL 131b066303fSPaul Burton * @gate: information valid if type includes CGU_CLK_GATE 132b066303fSPaul Burton * @mux: information valid if type includes CGU_CLK_MUX 133b066303fSPaul Burton * @div: information valid if type includes CGU_CLK_DIV 134b066303fSPaul Burton * @fixdiv: information valid if type includes CGU_CLK_FIXDIV 135b066303fSPaul Burton * @custom: information valid if type includes CGU_CLK_CUSTOM 136b066303fSPaul Burton */ 137b066303fSPaul Burton struct ingenic_cgu_clk_info { 138b066303fSPaul Burton const char *name; 139b066303fSPaul Burton 140b066303fSPaul Burton enum { 141b066303fSPaul Burton CGU_CLK_NONE = 0, 142b066303fSPaul Burton CGU_CLK_EXT = BIT(0), 143b066303fSPaul Burton CGU_CLK_PLL = BIT(1), 144b066303fSPaul Burton CGU_CLK_GATE = BIT(2), 145b066303fSPaul Burton CGU_CLK_MUX = BIT(3), 146b066303fSPaul Burton CGU_CLK_MUX_GLITCHFREE = BIT(4), 147b066303fSPaul Burton CGU_CLK_DIV = BIT(5), 148b066303fSPaul Burton CGU_CLK_FIXDIV = BIT(6), 149b066303fSPaul Burton CGU_CLK_CUSTOM = BIT(7), 150b066303fSPaul Burton } type; 151b066303fSPaul Burton 152b066303fSPaul Burton int parents[4]; 153b066303fSPaul Burton 154b066303fSPaul Burton union { 155b066303fSPaul Burton struct ingenic_cgu_pll_info pll; 156b066303fSPaul Burton 157b066303fSPaul Burton struct { 158b066303fSPaul Burton struct ingenic_cgu_gate_info gate; 159b066303fSPaul Burton struct ingenic_cgu_mux_info mux; 160b066303fSPaul Burton struct ingenic_cgu_div_info div; 161b066303fSPaul Burton struct ingenic_cgu_fixdiv_info fixdiv; 162b066303fSPaul Burton }; 163b066303fSPaul Burton 164b066303fSPaul Burton struct ingenic_cgu_custom_info custom; 165b066303fSPaul Burton }; 166b066303fSPaul Burton }; 167b066303fSPaul Burton 168b066303fSPaul Burton /** 169b066303fSPaul Burton * struct ingenic_cgu - data about the CGU 170b066303fSPaul Burton * @np: the device tree node that caused the CGU to be probed 171b066303fSPaul Burton * @base: the ioremap'ed base address of the CGU registers 172b066303fSPaul Burton * @clock_info: an array containing information about implemented clocks 173b066303fSPaul Burton * @clocks: used to provide clocks to DT, allows lookup of struct clk* 174b066303fSPaul Burton * @lock: lock to be held whilst manipulating CGU registers 175b066303fSPaul Burton */ 176b066303fSPaul Burton struct ingenic_cgu { 177b066303fSPaul Burton struct device_node *np; 178b066303fSPaul Burton void __iomem *base; 179b066303fSPaul Burton 180b066303fSPaul Burton const struct ingenic_cgu_clk_info *clock_info; 181b066303fSPaul Burton struct clk_onecell_data clocks; 182b066303fSPaul Burton 183b066303fSPaul Burton spinlock_t lock; 184b066303fSPaul Burton }; 185b066303fSPaul Burton 186b066303fSPaul Burton /** 187b066303fSPaul Burton * struct ingenic_clk - private data for a clock 1885fb94e9cSMauro Carvalho Chehab * @hw: see Documentation/driver-api/clk.rst 189b066303fSPaul Burton * @cgu: a pointer to the CGU data 190b066303fSPaul Burton * @idx: the index of this clock in cgu->clock_info 191b066303fSPaul Burton */ 192b066303fSPaul Burton struct ingenic_clk { 193b066303fSPaul Burton struct clk_hw hw; 194b066303fSPaul Burton struct ingenic_cgu *cgu; 195b066303fSPaul Burton unsigned idx; 196b066303fSPaul Burton }; 197b066303fSPaul Burton 198b066303fSPaul Burton #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) 199b066303fSPaul Burton 200b066303fSPaul Burton /** 201b066303fSPaul Burton * ingenic_cgu_new() - create a new CGU instance 202b066303fSPaul Burton * @clock_info: an array of clock information structures describing the clocks 203b066303fSPaul Burton * which are implemented by the CGU 204b066303fSPaul Burton * @num_clocks: the number of entries in clock_info 205b066303fSPaul Burton * @np: the device tree node which causes this CGU to be probed 206b066303fSPaul Burton * 207b066303fSPaul Burton * Return: a pointer to the CGU instance if initialisation is successful, 208b066303fSPaul Burton * otherwise NULL. 209b066303fSPaul Burton */ 210b066303fSPaul Burton struct ingenic_cgu * 211b066303fSPaul Burton ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, 212b066303fSPaul Burton unsigned num_clocks, struct device_node *np); 213b066303fSPaul Burton 214b066303fSPaul Burton /** 215b066303fSPaul Burton * ingenic_cgu_register_clocks() - Registers the clocks 216b066303fSPaul Burton * @cgu: pointer to cgu data 217b066303fSPaul Burton * 218b066303fSPaul Burton * Register the clocks described by the CGU with the common clock framework. 219b066303fSPaul Burton * 220b066303fSPaul Burton * Return: 0 on success or -errno if unsuccesful. 221b066303fSPaul Burton */ 222b066303fSPaul Burton int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); 223b066303fSPaul Burton 224b066303fSPaul Burton #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */ 225