1b066303fSPaul Burton /* 2b066303fSPaul Burton * Ingenic SoC CGU driver 3b066303fSPaul Burton * 4b066303fSPaul Burton * Copyright (c) 2013-2015 Imagination Technologies 5fb615d61SPaul Burton * Author: Paul Burton <paul.burton@mips.com> 6b066303fSPaul Burton * 7b066303fSPaul Burton * This program is free software; you can redistribute it and/or 8b066303fSPaul Burton * modify it under the terms of the GNU General Public License as 9b066303fSPaul Burton * published by the Free Software Foundation; either version 2 of 10b066303fSPaul Burton * the License, or (at your option) any later version. 11b066303fSPaul Burton * 12b066303fSPaul Burton * This program is distributed in the hope that it will be useful, 13b066303fSPaul Burton * but WITHOUT ANY WARRANTY; without even the implied warranty of 14b066303fSPaul Burton * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15b066303fSPaul Burton * GNU General Public License for more details. 16b066303fSPaul Burton */ 17b066303fSPaul Burton 18b066303fSPaul Burton #ifndef __DRIVERS_CLK_INGENIC_CGU_H__ 19b066303fSPaul Burton #define __DRIVERS_CLK_INGENIC_CGU_H__ 20b066303fSPaul Burton 21b066303fSPaul Burton #include <linux/bitops.h> 22b066303fSPaul Burton #include <linux/of.h> 23b066303fSPaul Burton #include <linux/spinlock.h> 24b066303fSPaul Burton 25b066303fSPaul Burton /** 26b066303fSPaul Burton * struct ingenic_cgu_pll_info - information about a PLL 27b066303fSPaul Burton * @reg: the offset of the PLL's control register within the CGU 28b066303fSPaul Burton * @m_shift: the number of bits to shift the multiplier value by (ie. the 29b066303fSPaul Burton * index of the lowest bit of the multiplier value in the PLL's 30b066303fSPaul Burton * control register) 31b066303fSPaul Burton * @m_bits: the size of the multiplier field in bits 32b066303fSPaul Burton * @m_offset: the multiplier value which encodes to 0 in the PLL's control 33b066303fSPaul Burton * register 34b066303fSPaul Burton * @n_shift: the number of bits to shift the divider value by (ie. the 35b066303fSPaul Burton * index of the lowest bit of the divider value in the PLL's 36b066303fSPaul Burton * control register) 37b066303fSPaul Burton * @n_bits: the size of the divider field in bits 38b066303fSPaul Burton * @n_offset: the divider value which encodes to 0 in the PLL's control 39b066303fSPaul Burton * register 40b066303fSPaul Burton * @od_shift: the number of bits to shift the post-VCO divider value by (ie. 41b066303fSPaul Burton * the index of the lowest bit of the post-VCO divider value in 42b066303fSPaul Burton * the PLL's control register) 43b066303fSPaul Burton * @od_bits: the size of the post-VCO divider field in bits 44b066303fSPaul Burton * @od_max: the maximum post-VCO divider value 45b066303fSPaul Burton * @od_encoding: a pointer to an array mapping post-VCO divider values to 46b066303fSPaul Burton * their encoded values in the PLL control register, or -1 for 47b066303fSPaul Burton * unsupported values 48b066303fSPaul Burton * @bypass_bit: the index of the bypass bit in the PLL control register 49b066303fSPaul Burton * @enable_bit: the index of the enable bit in the PLL control register 50b066303fSPaul Burton * @stable_bit: the index of the stable bit in the PLL control register 51268db077SPaul Cercueil * @no_bypass_bit: if set, the PLL has no bypass functionality 52b066303fSPaul Burton */ 53b066303fSPaul Burton struct ingenic_cgu_pll_info { 54b066303fSPaul Burton unsigned reg; 55b066303fSPaul Burton const s8 *od_encoding; 56b066303fSPaul Burton u8 m_shift, m_bits, m_offset; 57b066303fSPaul Burton u8 n_shift, n_bits, n_offset; 58b066303fSPaul Burton u8 od_shift, od_bits, od_max; 59b066303fSPaul Burton u8 bypass_bit; 60b066303fSPaul Burton u8 enable_bit; 61b066303fSPaul Burton u8 stable_bit; 62268db077SPaul Cercueil bool no_bypass_bit; 63b066303fSPaul Burton }; 64b066303fSPaul Burton 65b066303fSPaul Burton /** 66b066303fSPaul Burton * struct ingenic_cgu_mux_info - information about a clock mux 67b066303fSPaul Burton * @reg: offset of the mux control register within the CGU 68b066303fSPaul Burton * @shift: number of bits to shift the mux value by (ie. the index of 69b066303fSPaul Burton * the lowest bit of the mux value within its control register) 70b066303fSPaul Burton * @bits: the size of the mux value in bits 71b066303fSPaul Burton */ 72b066303fSPaul Burton struct ingenic_cgu_mux_info { 73b066303fSPaul Burton unsigned reg; 74b066303fSPaul Burton u8 shift; 75b066303fSPaul Burton u8 bits; 76b066303fSPaul Burton }; 77b066303fSPaul Burton 78b066303fSPaul Burton /** 79b066303fSPaul Burton * struct ingenic_cgu_div_info - information about a divider 80b066303fSPaul Burton * @reg: offset of the divider control register within the CGU 814afe2d1aSHarvey Hunt * @shift: number of bits to left shift the divide value by (ie. the index of 82b066303fSPaul Burton * the lowest bit of the divide value within its control register) 837ca4c922SPaul Cercueil * @div: number to divide the divider value by (i.e. if the 844afe2d1aSHarvey Hunt * effective divider value is the value written to the register 854afe2d1aSHarvey Hunt * multiplied by some constant) 86b066303fSPaul Burton * @bits: the size of the divide value in bits 87b066303fSPaul Burton * @ce_bit: the index of the change enable bit within reg, or -1 if there 88b066303fSPaul Burton * isn't one 89b066303fSPaul Burton * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one 90b066303fSPaul Burton * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one 91a9fa2893SPaul Cercueil * @div_table: optional table to map the value read from the register to the 92a9fa2893SPaul Cercueil * actual divider value 93b066303fSPaul Burton */ 94b066303fSPaul Burton struct ingenic_cgu_div_info { 95b066303fSPaul Burton unsigned reg; 96b066303fSPaul Burton u8 shift; 974afe2d1aSHarvey Hunt u8 div; 98b066303fSPaul Burton u8 bits; 99b066303fSPaul Burton s8 ce_bit; 100b066303fSPaul Burton s8 busy_bit; 101b066303fSPaul Burton s8 stop_bit; 102a9fa2893SPaul Cercueil const u8 *div_table; 103b066303fSPaul Burton }; 104b066303fSPaul Burton 105b066303fSPaul Burton /** 106b066303fSPaul Burton * struct ingenic_cgu_fixdiv_info - information about a fixed divider 107b066303fSPaul Burton * @div: the divider applied to the parent clock 108b066303fSPaul Burton */ 109b066303fSPaul Burton struct ingenic_cgu_fixdiv_info { 110b066303fSPaul Burton unsigned div; 111b066303fSPaul Burton }; 112b066303fSPaul Burton 113b066303fSPaul Burton /** 114b066303fSPaul Burton * struct ingenic_cgu_gate_info - information about a clock gate 115b066303fSPaul Burton * @reg: offset of the gate control register within the CGU 116b066303fSPaul Burton * @bit: offset of the bit in the register that controls the gate 1177ef3844fSPaul Cercueil * @clear_to_gate: if set, the clock is gated when the bit is cleared 118261a831fSPaul Cercueil * @delay_us: delay in microseconds after which the clock is considered stable 119b066303fSPaul Burton */ 120b066303fSPaul Burton struct ingenic_cgu_gate_info { 121b066303fSPaul Burton unsigned reg; 122b066303fSPaul Burton u8 bit; 1237ef3844fSPaul Cercueil bool clear_to_gate; 124261a831fSPaul Cercueil u16 delay_us; 125b066303fSPaul Burton }; 126b066303fSPaul Burton 127b066303fSPaul Burton /** 128b066303fSPaul Burton * struct ingenic_cgu_custom_info - information about a custom (SoC) clock 129b066303fSPaul Burton * @clk_ops: custom clock operation callbacks 130b066303fSPaul Burton */ 131b066303fSPaul Burton struct ingenic_cgu_custom_info { 132ee1f9df2SPaul Cercueil const struct clk_ops *clk_ops; 133b066303fSPaul Burton }; 134b066303fSPaul Burton 135b066303fSPaul Burton /** 136b066303fSPaul Burton * struct ingenic_cgu_clk_info - information about a clock 137b066303fSPaul Burton * @name: name of the clock 138b066303fSPaul Burton * @type: a bitmask formed from CGU_CLK_* values 139b066303fSPaul Burton * @parents: an array of the indices of potential parents of this clock 140b066303fSPaul Burton * within the clock_info array of the CGU, or -1 in entries 141b066303fSPaul Burton * which correspond to no valid parent 142b066303fSPaul Burton * @pll: information valid if type includes CGU_CLK_PLL 143b066303fSPaul Burton * @gate: information valid if type includes CGU_CLK_GATE 144b066303fSPaul Burton * @mux: information valid if type includes CGU_CLK_MUX 145b066303fSPaul Burton * @div: information valid if type includes CGU_CLK_DIV 146b066303fSPaul Burton * @fixdiv: information valid if type includes CGU_CLK_FIXDIV 147b066303fSPaul Burton * @custom: information valid if type includes CGU_CLK_CUSTOM 148b066303fSPaul Burton */ 149b066303fSPaul Burton struct ingenic_cgu_clk_info { 150b066303fSPaul Burton const char *name; 151b066303fSPaul Burton 152b066303fSPaul Burton enum { 153b066303fSPaul Burton CGU_CLK_NONE = 0, 154b066303fSPaul Burton CGU_CLK_EXT = BIT(0), 155b066303fSPaul Burton CGU_CLK_PLL = BIT(1), 156b066303fSPaul Burton CGU_CLK_GATE = BIT(2), 157b066303fSPaul Burton CGU_CLK_MUX = BIT(3), 158b066303fSPaul Burton CGU_CLK_MUX_GLITCHFREE = BIT(4), 159b066303fSPaul Burton CGU_CLK_DIV = BIT(5), 160b066303fSPaul Burton CGU_CLK_FIXDIV = BIT(6), 161b066303fSPaul Burton CGU_CLK_CUSTOM = BIT(7), 162b066303fSPaul Burton } type; 163b066303fSPaul Burton 164b066303fSPaul Burton int parents[4]; 165b066303fSPaul Burton 166b066303fSPaul Burton union { 167b066303fSPaul Burton struct ingenic_cgu_pll_info pll; 168b066303fSPaul Burton 169b066303fSPaul Burton struct { 170b066303fSPaul Burton struct ingenic_cgu_gate_info gate; 171b066303fSPaul Burton struct ingenic_cgu_mux_info mux; 172b066303fSPaul Burton struct ingenic_cgu_div_info div; 173b066303fSPaul Burton struct ingenic_cgu_fixdiv_info fixdiv; 174b066303fSPaul Burton }; 175b066303fSPaul Burton 176b066303fSPaul Burton struct ingenic_cgu_custom_info custom; 177b066303fSPaul Burton }; 178b066303fSPaul Burton }; 179b066303fSPaul Burton 180b066303fSPaul Burton /** 181b066303fSPaul Burton * struct ingenic_cgu - data about the CGU 182b066303fSPaul Burton * @np: the device tree node that caused the CGU to be probed 183b066303fSPaul Burton * @base: the ioremap'ed base address of the CGU registers 184b066303fSPaul Burton * @clock_info: an array containing information about implemented clocks 185b066303fSPaul Burton * @clocks: used to provide clocks to DT, allows lookup of struct clk* 186b066303fSPaul Burton * @lock: lock to be held whilst manipulating CGU registers 187b066303fSPaul Burton */ 188b066303fSPaul Burton struct ingenic_cgu { 189b066303fSPaul Burton struct device_node *np; 190b066303fSPaul Burton void __iomem *base; 191b066303fSPaul Burton 192b066303fSPaul Burton const struct ingenic_cgu_clk_info *clock_info; 193b066303fSPaul Burton struct clk_onecell_data clocks; 194b066303fSPaul Burton 195b066303fSPaul Burton spinlock_t lock; 196b066303fSPaul Burton }; 197b066303fSPaul Burton 198b066303fSPaul Burton /** 199b066303fSPaul Burton * struct ingenic_clk - private data for a clock 2005fb94e9cSMauro Carvalho Chehab * @hw: see Documentation/driver-api/clk.rst 201b066303fSPaul Burton * @cgu: a pointer to the CGU data 202b066303fSPaul Burton * @idx: the index of this clock in cgu->clock_info 203b066303fSPaul Burton */ 204b066303fSPaul Burton struct ingenic_clk { 205b066303fSPaul Burton struct clk_hw hw; 206b066303fSPaul Burton struct ingenic_cgu *cgu; 207b066303fSPaul Burton unsigned idx; 208b066303fSPaul Burton }; 209b066303fSPaul Burton 210b066303fSPaul Burton #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) 211b066303fSPaul Burton 212b066303fSPaul Burton /** 213b066303fSPaul Burton * ingenic_cgu_new() - create a new CGU instance 214b066303fSPaul Burton * @clock_info: an array of clock information structures describing the clocks 215b066303fSPaul Burton * which are implemented by the CGU 216b066303fSPaul Burton * @num_clocks: the number of entries in clock_info 217b066303fSPaul Burton * @np: the device tree node which causes this CGU to be probed 218b066303fSPaul Burton * 219b066303fSPaul Burton * Return: a pointer to the CGU instance if initialisation is successful, 220b066303fSPaul Burton * otherwise NULL. 221b066303fSPaul Burton */ 222b066303fSPaul Burton struct ingenic_cgu * 223b066303fSPaul Burton ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, 224b066303fSPaul Burton unsigned num_clocks, struct device_node *np); 225b066303fSPaul Burton 226b066303fSPaul Burton /** 227b066303fSPaul Burton * ingenic_cgu_register_clocks() - Registers the clocks 228b066303fSPaul Burton * @cgu: pointer to cgu data 229b066303fSPaul Burton * 230b066303fSPaul Burton * Register the clocks described by the CGU with the common clock framework. 231b066303fSPaul Burton * 232b066303fSPaul Burton * Return: 0 on success or -errno if unsuccesful. 233b066303fSPaul Burton */ 234b066303fSPaul Burton int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); 235b066303fSPaul Burton 236b066303fSPaul Burton #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */ 237